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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 | /* Copyright (c) 2022 Intel Corporation * SPDX-License-Identifier: Apache-2.0 */ /* * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. * * Functions here are designed to produce efficient code to * search an Xtensa bitmask of interrupts, inspecting only those bits * declared to be associated with a given interrupt level. Each * dispatcher will handle exactly one flagged interrupt, in numerical * order (low bits first) and will return a mask of that bit that can * then be cleared by the calling code. Unrecognized bits for the * level will invoke an error handler. */ #include <xtensa/config/core-isa.h> #include <zephyr/sys/util.h> #include <zephyr/sw_isr_table.h> #if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 #error core-isa.h interrupt level does not match dispatcher! #endif #if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 #error core-isa.h interrupt level does not match dispatcher! #endif #if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2 #error core-isa.h interrupt level does not match dispatcher! #endif #if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 2 #error core-isa.h interrupt level does not match dispatcher! #endif #if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2 #error core-isa.h interrupt level does not match dispatcher! #endif #if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 3 #error core-isa.h interrupt level does not match dispatcher! #endif #if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 3 #error core-isa.h interrupt level does not match dispatcher! #endif #if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 3 #error core-isa.h interrupt level does not match dispatcher! #endif #if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 5 #error core-isa.h interrupt level does not match dispatcher! #endif static inline int _xtensa_handle_one_int1(unsigned int mask) { int irq; if (mask & BIT(0)) { mask = BIT(0); irq = 0; goto handle_irq; } if (mask & BIT(1)) { mask = BIT(1); irq = 1; goto handle_irq; } return 0; handle_irq: _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); return mask; } static inline int _xtensa_handle_one_int2(unsigned int mask) { int irq; if (mask & BIT(2)) { mask = BIT(2); irq = 2; goto handle_irq; } if (mask & BIT(3)) { mask = BIT(3); irq = 3; goto handle_irq; } if (mask & BIT(4)) { mask = BIT(4); irq = 4; goto handle_irq; } return 0; handle_irq: _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); return mask; } static inline int _xtensa_handle_one_int3(unsigned int mask) { int irq; if (mask & BIT(5)) { mask = BIT(5); irq = 5; goto handle_irq; } if (mask & BIT(6)) { mask = BIT(6); irq = 6; goto handle_irq; } if (mask & BIT(7)) { mask = BIT(7); irq = 7; goto handle_irq; } return 0; handle_irq: _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); return mask; } static inline int _xtensa_handle_one_int5(unsigned int mask) { /* It is a Non-maskable interrupt handler. * The non-maskable interrupt have no corresponding bit in INTERRUPT and INTENABLE registers * so mask parameter is always 0. */ _sw_isr_table[8].isr(_sw_isr_table[8].arg); return 0; } static inline int _xtensa_handle_one_int0(unsigned int mask) { return 0; } static inline int _xtensa_handle_one_int4(unsigned int mask) { return 0; } |