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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 | # Copyright 2017-2024 NXP # SPDX-License-Identifier: Apache-2.0 if SOC_FAMILY_NXP_IMXRT # Source series Kconfig files first, so SOCs # can override the defaults given here rsource "*/Kconfig.defconfig" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX config SERIAL_INIT_PRIORITY default 55 if SERIAL depends on SERIAL config ROM_START_OFFSET default 0x400 if BOOTLOADER_MCUBOOT default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR config PINCTRL_IMX default y if HAS_MCUX_IOMUXC depends on PINCTRL config ADC_MCUX_12B1MSPS_SAR default y if HAS_MCUX_12B1MSPS_SAR depends on ADC config LOG_BACKEND_SWO_FREQ_HZ default 7500000 depends on LOG_BACKEND_SWO # set the tick per sec as a divider of the GPT clock source config SYS_CLOCK_TICKS_PER_SEC default 4096 if MCUX_GPT_TIMER DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk) config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMXRT10XX && CORTEX_M_SYSTICK default 32768 if MCUX_GPT_TIMER # Disable systick if using MCUX_GPT_TIMER, as they will conflict config CORTEX_M_SYSTICK default n if MCUX_GPT_TIMER config PM_MCUX_GPC default y if HAS_MCUX_GPC depends on SOC_SERIES_IMXRT11XX && PM # Don't allow SOC to sleep after tests complete when PM is enabled config ZTEST_NO_YIELD default y if (ZTEST && PM) if SOC_SERIES_IMXRT10XX && PM config CODE_DATA_RELOCATION default y config PM_MCUX_GPC default y if HAS_MCUX_GPC config PM_MCUX_DCDC default y if HAS_MCUX_DCDC config PM_MCUX_PMU default y if HAS_MCUX_PMU endif # SOC_SERIES_IMXRT10XX && PM if ETH_NXP_ENET config SYSTEM_WORKQUEUE_STACK_SIZE default 1560 endif # ETH_NXP_ENET config MEMC default y choice USB_MCUX_CONTROLLER_TYPE default USB_DC_NXP_EHCI endchoice DT_CHOSEN_Z_DTCM := zephyr,dtcm choice SEGGER_RTT_SECTION default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) depends on USE_SEGGER_RTT endchoice choice SEGGER_SYSVIEW_SECTION default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) depends on SEGGER_SYSTEMVIEW endchoice # # MBEDTLS is larger but much faster than TinyCrypt so choose wisely # config MBEDTLS #config TINYCRYPT default y if CSPRNG_ENABLED depends on ENTROPY_GENERATOR if MBEDTLS # # MBEDTLS CTR_DRBG code path needs extra stack space for initialization than # what the ztest_thread_stack defaults to. # config TEST_EXTRA_STACK_SIZE int default 1024 endif # MBEDTLS # Enable cache management features when using M7 core, since these parts # have L1 instruction and data caches that should be enabled at boot config CACHE_MANAGEMENT default y if CPU_CORTEX_M7 endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX # Logic to set flash size for all IMXRT parts DT_CHOSEN_Z_FLASH := zephyr,flash DT_COMPAT_FLEXSPI := nxp,imx-flexspi DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) config FLASH_BASE_ADDRESS default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ if $(DT_FLASH_PARENT_IS_FLEXSPI) config FLASH_SIZE default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ if $(DT_FLASH_HAS_SIZE_PROP) if FLASH_MCUX_FLEXSPI_XIP # Avoid RWW hazards by defaulting logging to disabled choice FLASH_LOG_LEVEL_CHOICE default FLASH_LOG_LEVEL_OFF endchoice choice MEMC_LOG_LEVEL_CHOICE default MEMC_LOG_LEVEL_OFF endchoice endif endif # SOC_FAMILY_NXP_IMXRT |