/*
 * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
 * Copyright (c) 2022 Georgij Cernysiov <geo.cgv@gmail.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <st/h7/stm32h7.dtsi>
#include <zephyr/dt-bindings/display/panel.h>
#include <zephyr/dt-bindings/flash_controller/ospi.h>

/ {
	soc {
		compatible = "st,stm32h723", "st,stm32h7", "simple-bus";

		flash-controller@52002000 {
			flash0: flash@8000000 {
				compatible = "st,stm32-nv-flash", "soc-nv-flash";
				write-block-size = <32>;
				erase-block-size = <DT_SIZE_K(128)>;
				/* maximum erase time for a 128K sector */
				max-erase-time = <4000>;
			};
		};

		uart9: serial@40011800 {
			compatible = "st,stm32-uart";
			reg = <0x40011800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
			resets = <&rctl STM32_RESET(APB2, 6U)>;
			interrupts = <155 0>;
			status = "disabled";
		};

		usart10: serial@40011c00 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
			resets = <&rctl STM32_RESET(APB2, 7U)>;
			interrupts = <156 0>;
			status = "disabled";
		};

		/*
		 * ADC3 on STM32H723, 725, 730, 733 & 735 is a 12-bit resolution
		 * ADC, so we redefine the resolution for these devices.
		 */
		adc3: adc@58026000 {
			resolutions = <STM32H72X_ADC3_RES(12, 0x00)
				       STM32H72X_ADC3_RES(10, 0x01)
				       STM32H72X_ADC3_RES(8, 0x02)
				       STM32H72X_ADC3_RES(6, 0x03)>;
			sampling-times = <3 7 13 25 48 93 248 641>;
			st,adc-sequencer = <FULLY_CONFIGURABLE>;
		};

		dmamux1: dmamux@40020800 {
			dma-requests= <129>;
		};

		dmamux2: dmamux@58025800 {
			dma-requests= <129>;
		};

		rng: rng@48021800 {
			health-test-magic = <0x17590abc>;
			health-test-config = <0xaa74>;
		};

		usbotg_hs: usb@40040000 {
			compatible = "st,stm32-otghs";
			reg = <0x40040000 0x40000>;
			interrupts = <77 0>, <74 0>, <75 0>;
			interrupt-names = "otghs", "ep1_out", "ep1_in";
			num-bidir-endpoints = <9>;
			ram-size = <DT_SIZE_K(4)>;
			maximum-speed = "full-speed";
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
			phys = <&otghs_fs_phy>;
			status = "disabled";
		};

		ltdc: display-controller@50001000 {
			compatible = "st,stm32-ltdc";
			reg = <0x50001000 0x200>;
			interrupts = <88 0>, <89 0>;
			interrupt-names = "ltdc", "ltdc_er";
			clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
			status = "disabled";
		};

		octospi1: octospi@52005000 {
			compatible = "st,stm32-ospi";
			reg = <0x52005000 0x1000>;
			interrupts = <92 0>;
			clock-names = "ospix", "ospi-ker";
			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00004000>,
				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		octospi2: octospi@5200a000 {
			compatible = "st,stm32-ospi";
			reg = <0x5200a000 0x1000>;
			interrupts = <150 0>;
			clock-names = "ospix", "ospi-ker";
			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x000080000>,
				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		fdcan3: can@4000d400 {
			compatible = "st,stm32h7-fdcan";
			reg = <0x4000d400 0x400>, <0x4000ac00 0x9f0>;
			reg-names = "m_can", "message_ram";
			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>;
			interrupts = <159 0>, <160 0>, <63 0>;
			interrupt-names = "int0", "int1", "calib";
			bosch,mram-cfg = <0x6a0 28 8 3 3 0 3 3>;
			sample-point = <875>;
			sample-point-data = <875>;
			status = "disabled";
		};

		rtc@58004000 {
			bbram: backup_regs {
				compatible = "st,stm32-bbram";
				st,backup-regs = <32>;
				status = "disabled";
			};
		};
	};

	/* D1 domain, AXI SRAM (128KB with shared ITCM 192KB as `TCM_AXI_SHARED` is `000`) */
	sram0: memory@24000000 {
		reg = <0x24000000 DT_SIZE_K(320)>;
		compatible = "mmio-sram";
	};

	/* D2 domain, AHB SRAM */
	sram1: memory@30000000 {
		reg = <0x30000000 DT_SIZE_K(16)>;
		compatible = "zephyr,memory-region", "mmio-sram";
		zephyr,memory-region = "SRAM1";
	};

	/* D2 domain, AHB SRAM */
	sram2: memory@30004000 {
		reg = <0x30004000 DT_SIZE_K(16)>;
		compatible = "zephyr,memory-region", "mmio-sram";
		zephyr,memory-region = "SRAM2";
	};

	/* D3 domain, AHB SRAM  */
	sram4: memory@38000000 {
		reg = <0x38000000 DT_SIZE_K(16)>;
		compatible = "zephyr,memory-region", "mmio-sram";
		zephyr,memory-region = "SRAM4";
	};

	/* Data TCM RAM */
	dtcm: memory@20000000 {
		compatible = "zephyr,memory-region", "arm,dtcm";
		reg = <0x20000000 DT_SIZE_K(128)>;
		zephyr,memory-region = "DTCM";
	};

	/* Instruction TCM RAM (64KB as `TCM_AXI_SHARED` is `000`) */
	itcm: memory@0 {
		compatible = "zephyr,memory-region", "arm,itcm";
		reg = <0x00000000 DT_SIZE_K(64)>;
		zephyr,memory-region = "ITCM";
	};

	otghs_fs_phy: otghs_fs_phy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};

	die_temp: dietemp {
		io-channels = <&adc3 17>;
		ts-cal2-temp = <130>;
	};

	vref: vref {
		io-channels = <&adc3 18>;
	};

	vbat: vbat {
		io-channels = <&adc3 16>;
	};
};