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/* * Copyright (c) 2021 The Chromium OS Authors * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com> * Copyright (c) 2019 ST Microelectronics * * SPDX-License-Identifier: Apache-2.0 */ #include <st/g0/stm32g051.dtsi> / { soc { compatible = "st,stm32g071", "st,stm32g0", "simple-bus"; usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; resets = <&rctl STM32_RESET(APB1L, 18U)>; interrupts = <29 0>; status = "disabled"; }; usart4: serial@40004c00 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; resets = <&rctl STM32_RESET(APB1L, 19U)>; interrupts = <29 0>; status = "disabled"; }; dmamux1: dmamux@40020800 { dma-requests= <57>; }; ucpd1: ucpd@4000a000 { compatible = "st,stm32-ucpd"; reg = <0x4000a000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>; interrupts = <8 0>; status = "disabled"; }; ucpd2: ucpd@4000a400 { compatible = "st,stm32-ucpd"; reg = <0x4000a400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>; interrupts = <8 0>; status = "disabled"; }; }; }; |