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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 | /* * Copyright (c) 2018 Seitz & Associates * * SPDX-License-Identifier: Apache-2.0 */ #include <st/f3/stm32f3.dtsi> #include <zephyr/dt-bindings/adc/stm32l4_adc.h> / { soc { compatible = "st,stm32f302", "st,stm32f3", "simple-bus"; usb: usb@40005c00 { /* Remap USB_LP IRQ to enable use with CAN_1 */ interrupts = <75 0>; }; i2c2: i2c@40005800 { compatible = "st,stm32-i2c-v2"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>, /* I2C clock source should always be defined, * even for the default value */ <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; }; i2c3: i2c@40007800 { compatible = "st,stm32-i2c-v2"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40007800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>, /* I2C clock source should always be defined, * even for the default value */ <&rcc STM32_SRC_SYSCLK I2C3_SEL(1)>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; status = "disabled"; }; spi2: spi@40003800 { compatible = "st,stm32-spi-fifo", "st,stm32-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; interrupts = <36 5>; status = "disabled"; }; spi3: spi@40003c00 { compatible = "st,stm32-spi-fifo", "st,stm32-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0X40003c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; interrupts = <51 5>; status = "disabled"; }; timers1: timers@40012c00 { compatible = "st,stm32-timers"; reg = <0x40012c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>; resets = <&rctl STM32_RESET(APB2, 11U)>; interrupts = <24 0>, <25 0>, <26 0>, <27 0>; interrupt-names = "brk", "up", "trgcom", "cc"; st,prescaler = <0>; status = "disabled"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; #pwm-cells = <3>; }; }; timers4: timers@40000800 { compatible = "st,stm32-timers"; reg = <0x40000800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; resets = <&rctl STM32_RESET(APB1, 2U)>; interrupts = <30 0>; interrupt-names = "global"; st,prescaler = <0>; status = "disabled"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; #pwm-cells = <3>; }; }; adc1: adc@50000000 { compatible = "st,stm32-adc"; reg = <0x50000000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>; interrupts = <18 0>; status = "disabled"; #io-channel-cells = <1>; resolutions = <STM32_ADC_RES(12, 0x00) STM32_ADC_RES(10, 0x01) STM32_ADC_RES(8, 0x02) STM32_ADC_RES(6, 0x03)>; sampling-times = <2 3 5 8 20 62 182 602>; st,adc-sequencer = <FULLY_CONFIGURABLE>; }; }; }; |