Linux Audio

Check our new training course

Loading...
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
/*
 * Copyright 2022 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv8-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <3>;
		};

		cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <4>;
		};

		cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <5>;
		};

		cpu@6 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <6>;
		};

		cpu@7 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <7>;
		};
	};

	arch_timer: timer {
		compatible = "arm,armv8_timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
	};

	/* Dummy pinctrl node, filled with pin mux options at board level */
	pinctrl: pinctrl {
		compatible = "nxp,s32ze-pinctrl";
		status = "okay";
	};

	soc {
		interrupt-parent = <&gic>;

		gic: interrupt-controller@47800000 {
			compatible = "arm,gic";
			reg = <0x47800000 0x10000>,
				<0x47900000 0x80000>;
			interrupt-controller;
			#interrupt-cells = <4>;
			status = "okay";
		};

		sram0: memory@31780000 {
			compatible = "mmio-sram";
			reg = <0x31780000 DT_SIZE_M(1)>;
		};

		sram1: memory@35780000 {
			compatible = "mmio-sram";
			reg = <0x35780000 DT_SIZE_M(1)>;
		};

		uart0: uart@40170000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40170000 0x1000>;
			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart1: uart@40180000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40180000 0x1000>;
			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart2: uart@40190000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40190000 0x1000>;
			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart3: uart@40970000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40970000 0x1000>;
			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart4: uart@40980000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40980000 0x1000>;
			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart5: uart@40990000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40990000 0x1000>;
			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart6: uart@42170000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42170000 0x1000>;
			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart7: uart@42180000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42180000 0x1000>;
			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart8: uart@42190000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42190000 0x1000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart9: uart@42980000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42980000 0x1000>;
			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart10: uart@42990000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x42990000 0x1000>;
			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart11: uart@429a0000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x429a0000 0x1000>;
			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		uart12: uart@40330000 {
			compatible = "nxp,s32-linflexd";
			reg = <0x40330000 0x1000>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			status = "disabled";
		};

		siul2_0: siul2@40520000 {
			reg = <0x40520000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			eirq0: eirq0@40520010 {
				compatible = "nxp,s32-siul2-eirq";
				reg = <0x40520010 0x04>, <0x40520018 0x04>;
				reg-names = "disr0", "direr0";
				interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpioa: gpio@40521702 {
				compatible = "nxp,s32-gpio";
				reg = <0x40521702 0x02>, <0x40520240 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq0>;
				interrupts = <1 1>, <3 0>, <5 2>, <12 3>,
						<13 4>, <14 5>, <15 6>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiob: gpio@40521700 {
				compatible = "nxp,s32-gpio";
				reg = <0x40521700 0x02>, <0x40520280 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq0>;
				interrupts = <0 7>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <15>;
				status = "disabled";
			};

			gpioo: gpio@40521716 {
				compatible = "nxp,s32-gpio";
				reg = <0x40521716 0x02>, <0x405204c0 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <14>;
				gpio-reserved-ranges = <0 10>;
				status = "disabled";
			};
		};

		siul2_1: siul2@40d20000 {
			reg = <0x40d20000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			eirq1: eirq1@40d20010 {
				compatible = "nxp,s32-siul2-eirq";
				reg = <0x40d20010 0x04>, <0x40d20018 0x04>;
				reg-names = "disr0", "direr0";
				interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpioc: gpio@40d21700 {
				compatible = "nxp,s32-gpio";
				reg = <0x40d21700 0x02>, <0x40d20280 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq1>;
				interrupts = <3 0>, <5 1>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				gpio-reserved-ranges = <0 15>;
				status = "disabled";
			};

			gpiod: gpio@40d21706 {
				compatible = "nxp,s32-gpio";
				reg = <0x40d21706 0x02>, <0x40d202c0 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpioe: gpio@40d21704 {
				compatible = "nxp,s32-gpio";
				reg = <0x40d21704 0x02>, <0x40d20300 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiof: gpio@40d2170a {
				compatible = "nxp,s32-gpio";
				reg = <0x40d2170a 0x02>, <0x40d20340 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiog: gpio@40d21708 {
				compatible = "nxp,s32-gpio";
				reg = <0x40d21708 0x02>, <0x40d20380 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq1>;
				interrupts = <0 2>, <1 3>, <4 4>,
						<5 5>, <10 6>, <11 7>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <12>;
				status = "disabled";
			};
		};

		siul2_3: siul2@41d20000 {
			reg = <0x41d20000 0x10000>;
		};

		siul2_4: siul2@42520000 {
			reg = <0x42520000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			eirq4: eirq4@42520010 {
				compatible = "nxp,s32-siul2-eirq";
				reg = <0x42520010 0x04>, <0x42520018 0x04>;
				reg-names = "disr0", "direr0";
				interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpioh: gpio@42521708 {
				compatible = "nxp,s32-gpio";
				reg = <0x42521708 0x02>, <0x42520380 0x40>;
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				gpio-reserved-ranges = <0 12>;
				status = "disabled";
			};

			gpioi: gpio@4252170e {
				compatible = "nxp,s32-gpio";
				reg = <0x4252170e 0x02>, <0x425203c0 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq4>;
				interrupts = <11 0>, <13 1>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpioj: gpio@4252170c {
				compatible = "nxp,s32-gpio";
				reg = <0x4252170c 0x02>, <0x42520400 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq4>;
				interrupts = <12 2>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiok: gpio@42521712 {
				compatible = "nxp,s32-gpio";
				reg = <0x42521712 0x02>, <0x42520440 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq4>;
				interrupts = <4 3>, <6 4>, <9 5>,
						<11 6>, <13 7>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				status = "disabled";
			};

			gpiol: gpio@42521710 {
				compatible = "nxp,s32-gpio";
				reg = <0x42521710 0x02>, <0x42520480 0x40>;
				reg-names = "disr0", "direr0";
				reg-names = "pgpdo", "mscr";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <2>;
				status = "disabled";
			};
		};

		siul2_5: siul2@42d20000 {
			reg = <0x42d20000 0x10000>;
			#address-cells = <1>;
			#size-cells = <1>;

			eirq5: eirq5@42d20010 {
				compatible = "nxp,s32-siul2-eirq";
				reg = <0x42d20010 0x04>, <0x42d20018 0x04>;
				reg-names = "disr0", "direr0";
				interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
				interrupt-controller;
				#interrupt-cells = <2>;
				status = "disabled";
			};

			gpiom: gpio@42d21710 {
				compatible = "nxp,s32-gpio";
				reg = <0x42d21710 0x02>, <0x42d20480 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq5>;
				interrupts = <1 0>, <3 1>, <5 2>, <7 3>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <16>;
				gpio-reserved-ranges = <0 2>;
				status = "disabled";
			};

			gpion: gpio@42d21716 {
				compatible = "nxp,s32-gpio";
				reg = <0x42d21716 0x02>, <0x42d204c0 0x40>;
				reg-names = "pgpdo", "mscr";
				interrupt-parent = <&eirq5>;
				interrupts = <0 4>, <2 5>, <5 6>, <6 7>;
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <10>;
				status = "disabled";
			};
		};

		spi0: spi@40130000 {
			compatible = "nxp,s32-spi";
			reg = <0x40130000 0x10000>;
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@40140000 {
			compatible = "nxp,s32-spi";
			reg = <0x40140000 0x10000>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@40930000 {
			compatible = "nxp,s32-spi";
			reg = <0x40930000 0x10000>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi3: spi@40940000 {
			compatible = "nxp,s32-spi";
			reg = <0x40940000 0x10000>;
			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi4: spi@40950000 {
			compatible = "nxp,s32-spi";
			reg = <0x40950000 0x10000>;
			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi5: spi@42130000 {
			compatible = "nxp,s32-spi";
			reg = <0x42130000 0x10000>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi6: spi@42140000 {
			compatible = "nxp,s32-spi";
			reg = <0x42140000 0x10000>;
			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi7: spi@42150000 {
			compatible = "nxp,s32-spi";
			reg = <0x42150000 0x10000>;
			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi8: spi@42930000 {
			compatible = "nxp,s32-spi";
			reg = <0x42930000 0x10000>;
			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi9: spi@42940000 {
			compatible = "nxp,s32-spi";
			reg = <0x42940000 0x10000>;
			interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			num-cs = <5>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		mru0: mbox@76070000 {
			compatible = "nxp,s32-mru";
			reg = <0x76070000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru1: mbox@76090000 {
			compatible = "nxp,s32-mru";
			reg = <0x76090000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru2: mbox@76270000 {
			compatible = "nxp,s32-mru";
			reg = <0x76270000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru3: mbox@76290000 {
			compatible = "nxp,s32-mru";
			reg = <0x76290000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru4: mbox@76870000 {
			compatible = "nxp,s32-mru";
			reg = <0x76870000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru5: mbox@76890000 {
			compatible = "nxp,s32-mru";
			reg = <0x76890000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru6: mbox@76a70000 {
			compatible = "nxp,s32-mru";
			reg = <0x76a70000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		mru7: mbox@76a90000 {
			compatible = "nxp,s32-mru";
			reg = <0x76a90000 0x10000>;
			interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			#mbox-cells = <1>;
			status = "disabled";
		};

		netc: ethernet@74000000 {
			reg = <0x74000000 0x1000000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			emdio: mdio@74b60000 {
				compatible = "nxp,s32-netc-emdio";
				reg = <0x74b60000 0x1c44>;
				status = "disabled";
			};

			enetc_psi0: ethernet@74b00000 {
				compatible = "nxp,s32-netc-psi";
				reg = <0x74b00000 0x10000>;
				status = "disabled";
			};

			enetc_vsi1: ethernet@74bc0000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74bc0000 0x10000>;
				status = "disabled";
			};

			enetc_vsi2: ethernet@74bd0000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74bd0000 0x10000>;
				status = "disabled";
			};

			enetc_vsi3: ethernet@74be0000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74be0000 0x10000>;
				status = "disabled";
			};

			enetc_vsi4: ethernet@74bf0000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74bf0000 0x10000>;
				status = "disabled";
			};

			enetc_vsi5: ethernet@74c00000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74c00000 0x10000>;
				status = "disabled";
			};

			enetc_vsi6: ethernet@74c10000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74c10000 0x10000>;
				status = "disabled";
			};

			enetc_vsi7: ethernet@74c20000 {
				compatible = "nxp,s32-netc-vsi";
				reg = <0x74c20000 0x10000>;
				status = "disabled";
			};
		};

		can0: can@4741b000 {
			compatible = "nxp,s32-canxl";
			reg = <0x4741b000 0x4000>,
				<0x47426000 0x4000>,
				<0x47424000 0x4000>;
			reg-names = "sic", "grp_ctrl", "dsc_ctrl";
			status = "disabled";
			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 225 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			interrupt-names = "RX_TX_DATA_IRQ", "INT_ERROR_IRQ";
		};

		can1: can@4751b000 {
			compatible = "nxp,s32-canxl";
			reg = <0x4751b000 0x4000>,
				<0x47526000 0x4000>,
				<0x47524000 0x4000>;
			reg-names = "sic", "grp_ctrl", "dsc_ctrl";
			status = "disabled";
			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 227 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			interrupt-names = "RX_TX_DATA_IRQ", "INT_ERROR_IRQ";
		};
	};
};