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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 | /* * Copyright (c) 2019 Brett Witherspoon * * SPDX-License-Identifier: Apache-2.0 */ #include <arm/armv7-m.dtsi> #include <zephyr/dt-bindings/i2c/i2c.h> #include <zephyr/dt-bindings/gpio/gpio.h> / { chosen { zephyr,entropy = &trng; zephyr,flash-controller = &flash_controller; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m4"; reg = <0>; }; }; sram0: memory@20000000 { compatible = "mmio-sram"; }; /* VIMS RAM configurable in CCFG as GPRAM or cache for FLASH (default) */ sram1: memory@11000000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x11000000 0x2000>; zephyr,memory-region = "SRAM1"; }; sysclk: system-clock { compatible = "fixed-clock"; clock-frequency = <48000000>; #clock-cells = <0>; }; soc { pinctrl: pinctrl@40081000 { compatible = "ti,cc13xx-cc26xx-pinctrl"; reg = <0x40081000 0x1000>; }; gpio0: gpio@40022000 { compatible = "ti,cc13xx-cc26xx-gpio"; reg = <0x40022000 0x400>; interrupts = <0 0>; status = "disabled"; gpio-controller; #gpio-cells = <2>; }; trng: random@40028000 { compatible = "ti,cc13xx-cc26xx-trng"; reg = <0x40028000 0x2000>; interrupts = <33 0>; status = "disabled"; }; flash_controller: flash-controller@40030000 { compatible = "ti,cc13xx-cc26xx-flash-controller"; reg = <0x40030000 0x4000>; #address-cells = <1>; #size-cells = <1>; flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <DT_SIZE_K(8)>; write-block-size = <1>; }; }; uart0: uart@40001000 { compatible = "ti,cc13xx-cc26xx-uart"; reg = <0x40001000 0x1000>; interrupts = <5 0>; clocks = <&sysclk>; status = "disabled"; }; uart1: uart@4000b000 { compatible = "ti,cc13xx-cc26xx-uart"; reg = <0x4000b000 0x1000>; interrupts = <36 0>; clocks = <&sysclk>; status = "disabled"; }; i2c0: i2c@40002000 { compatible = "ti,cc13xx-cc26xx-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x40002000 0x1000>; interrupts = <1 0>; clock-frequency = <I2C_BITRATE_STANDARD>; status = "disabled"; }; spi0: spi@40000000 { compatible = "ti,cc13xx-cc26xx-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40000000 0x1000>; interrupts = <7 0>; status = "disabled"; }; spi1: spi@40008000 { compatible = "ti,cc13xx-cc26xx-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40008000 0x1000>; interrupts = <8 0>; status = "disabled"; }; rtc: rtc@40092000 { compatible = "ti,cc13xx-cc26xx-rtc"; reg = <0x40092000 0x1000>; interrupts = <4 0>; /* interrupt #20 = 4 + 16 */ status = "disabled"; }; radio: radio@40040000 { compatible = "ti,cc13xx-cc26xx-radio"; status = "disabled"; reg = <0x40040000 0x1000 0x40041000 0x2000 0x40043000 0x1000 0x40044000 0x1000>; reg-names = "RFC_PWR", "RFC_DBELL", "RFC_RAT", "RFC_FSCA"; ieee802154: ieee802154 { compatible = "ti,cc13xx-cc26xx-ieee802154"; status = "disabled"; }; ieee802154g: ieee802154g { compatible = "ti,cc13xx-cc26xx-ieee802154-subghz"; status = "disabled"; }; }; wdt0: watchdog@40080000 { compatible = "ti,cc13xx-cc26xx-watchdog"; reg = <0x40080000 0x1000>; interrupts = <14 0>; /* interrupt #30 = 14 + 16 */ status = "disabled"; }; adc0: adc@400cb008 { compatible = "ti,cc13xx-cc26xx-adc"; reg = <0x400cb008 0x1>; interrupts = <32 0>; /* interrupt #48 = 32 + 16 */ status = "disabled"; #io-channel-cells = <1>; }; }; }; &nvic { arm,num-irq-priority-bits = <3>; }; &systick { status = "disabled"; }; |