/*
 * Copyright 2021 The Chromium OS Authors
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;
#include <st/g0/stm32g081Xb.dtsi>
#include <st/g0/stm32g081rbtx-pinctrl.dtsi>

/ {
	model = "STM32G081B EVAL board";
	compatible = "st,stm32g081-eval";

	chosen {
		zephyr,console = &usart3;
		zephyr,shell-uart = &usart3;
		zephyr,sram = &sram0;
		zephyr,flash = &flash0;
	};

	leds {
		compatible = "gpio-leds";
		led_1: led1 {
			gpios = <&gpiod 5 GPIO_ACTIVE_HIGH>;
			label = "LED1";
		};
		led_2: led2 {
			gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>;
			label = "LED2";
		};
		led_3: led3 {
			gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
			label = "LED3";
		};
		led_4: led4 {
			gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
			label = "LED4";
		};
	};

	gpio_keys {
		compatible = "gpio-keys";
		joy_sel: button0 {
			label = "JOY_SEL";
			gpios = <&gpioa 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
		};
		joy_left: button1 {
			label = "JOY_LEFT";
			gpios = <&gpioc 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
		};
		joy_down: button2 {
			label = "JOY_DOWN";
			gpios = <&gpioc 3 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
		};
		joy_right: button3 {
			label = "JOY_RIGHT";
			gpios = <&gpioc 7 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
		};
		joy_up: button4 {
			label = "JOY_UP";
			gpios = <&gpioc 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
		};
	};

	aliases {
		led0 = &led_1;
		led1 = &led_2;
		led2 = &led_3;
		led3 = &led_4;
		sw0 = &joy_sel;
		sw1 = &joy_left;
		sw2 = &joy_down;
		sw3 = &joy_right;
		sw4 = &joy_up;
		watchdog0 = &iwdg;
	};
};

&clk_hsi {
	status = "okay";
};

&pll {
	div-m = <1>;
	mul-n = <8>;
	div-p = <2>;
	div-q = <2>;
	div-r = <2>;
	clocks = <&clk_hsi>;
	status = "okay";
};

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(64)>;
	ahb-prescaler = <1>;
	apb1-prescaler = <1>;
};

&usart3 {
	pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>;
	pinctrl-names = "default";
	current-speed = <115200>;
	status = "okay";
};

&tim15_ch1_pc1 {
	slew-rate = "very-high-speed";
	bias-pull-up;
	drive-open-drain;
};

&timers15 {
	status = "okay";
	pwm15: pwm {
		status = "okay";
		pinctrl-0 = <&tim15_ch1_pc1>;
		pinctrl-names = "default";
	};
};

&adc1 {
	pinctrl-0 = <&adc1_in3_pa3 &adc1_in9_pb1>;
	pinctrl-names = "default";
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;

	channel@3 {
		reg = <3>;
		zephyr,gain = "ADC_GAIN_1";
		zephyr,reference = "ADC_REF_INTERNAL";
		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
		zephyr,resolution = <12>;
		zephyr,vref-mv = <3300>;
	};

	channel@9 {
		reg = <9>;
		zephyr,gain = "ADC_GAIN_1";
		zephyr,reference = "ADC_REF_INTERNAL";
		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
		zephyr,resolution = <12>;
		zephyr,vref-mv = <3300>;
	};
};

&ucpd1 {
	status = "okay";

	/*
	 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
	 * a prescaler who's output feeds the 'half-bit' divider which is used
	 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
	 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
	 * range is 9 <--> 18 MHz.
	 *
	 *          +-------+ @ 16 MHz +-------+   @ ~600 kHz   +-----------+
	 * HSI ---->| /psc  |--------->| /hbit |--------------->| trans_cnt |
	 *          +-------+          +-------+   |            +-----------+
	 *                                         |            +-----------+
	 *                                         +----------->| ifrgap_cnt|
	 *                                                      +-----------+
	 * Requirements:
	 *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
	 *   2. tTransitionWindow - 12 to 20 uSec
	 *   3. tInterframGap - uSec
	 *
	 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
	 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
	 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
	 */
	psc-ucpdclk = <1>;
	hbitclkdiv = <27>;
	pinctrl-0 = <&ucpd1_cc1_pa8 &ucpd1_cc2_pb15>;
	pinctrl-names = "default";
};

&ucpd2 {
	status = "okay";

	/*
	 * UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
	 * a prescaler who's output feeds the 'half-bit' divider which is used
	 * to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
	 * designed to work in freq ranges of 6 <--> 18 MHz, however recommended
	 * range is 9 <--> 18 MHz.
	 *
	 *          +-------+ @ 16 MHz +-------+   @ ~600 kHz   +-----------+
	 * HSI ---->| /psc  |--------->| /hbit |--------------->| trans_cnt |
	 *          +-------+          +-------+   |            +-----------+
	 *                                         |            +-----------+
	 *                                         +----------->| ifrgap_cnt|
	 *                                                      +-----------+
	 * Requirements:
	 *   1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
	 *   2. tTransitionWindow - 12 to 20 uSec
	 *   3. tInterframGap - uSec
	 *
	 * hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
	 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
	 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
	 */
	psc-ucpdclk = <1>;
	hbitclkdiv = <27>;
	pinctrl-0 = <&ucpd2_cc1_pd0 &ucpd2_cc2_pd2>;
	pinctrl-names = "default";
};

&iwdg {
	status = "okay";
};