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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 | /* * Copyright (c) 2019 STMicroelectronics * Copyright (c) 2019 Centaur Analytics, Inc * * SPDX-License-Identifier: Apache-2.0 */ #include <mem.h> #include <freq.h> #include <arm/armv7-m.dtsi> #include <zephyr/dt-bindings/gpio/gpio.h> #include <zephyr/dt-bindings/clock/stm32_clock.h> #include <zephyr/dt-bindings/i2c/i2c.h> #include <zephyr/dt-bindings/pwm/pwm.h> #include <zephyr/dt-bindings/pwm/stm32_pwm.h> #include <zephyr/dt-bindings/display/stm32_ltdc.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m4"; reg = <0>; }; }; retram: memory0@0 { compatible = "mmio-sram"; reg = <0x00000000 DT_SIZE_K(64)>; }; mcusram: memory1@10000000 { compatible = "mmio-sram"; reg = <0x10000000 DT_SIZE_K(320)>; }; soc { rcc: rcc@50000000 { compatible = "st,stm32mp1-rcc"; reg = <0x50000000 0x1000>; #clock-cells = <2>; }; exti: interrupt-controller@5000d000 { compatible = "st,stm32-exti"; interrupt-controller; #interrupt-cells = <1>; reg = <0x5000d000 0x400>; }; pinctrl: pin-controller@50002000 { compatible = "st,stm32-pinctrl"; reg = <0x50002000 0x9000>; #address-cells = <1>; #size-cells = <1>; gpioa: gpio@50002000 { compatible = "st,stm32-gpio"; reg = <0x50002000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>; }; gpiob: gpio@50003000 { compatible = "st,stm32-gpio"; reg = <0x50003000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>; }; gpioc: gpio@50004000 { compatible = "st,stm32-gpio"; reg = <0x50004000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>; }; gpiod: gpio@50005000 { compatible = "st,stm32-gpio"; reg = <0x50005000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>; }; gpioe: gpio@50006000 { compatible = "st,stm32-gpio"; reg = <0x50006000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>; }; gpiof: gpio@50007000 { compatible = "st,stm32-gpio"; reg = <0x50007000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>; }; gpiog: gpio@50008000 { compatible = "st,stm32-gpio"; reg = <0x50008000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>; }; gpioh: gpio@50009000 { compatible = "st,stm32-gpio"; reg = <0x50009000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>; }; gpioi: gpio@5000a000 { compatible = "st,stm32-gpio"; reg = <0x5000a000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>; }; gpioj: gpio@5000b000 { compatible = "st,stm32-gpio"; reg = <0x5000b000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>; }; gpiok: gpio@5000c000 { compatible = "st,stm32-gpio"; reg = <0x5000c000 0x400>; gpio-controller; #gpio-cells = <2>; clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>; }; }; wwdg: wwdg1: watchdog@4000a000 { compatible = "st,stm32-window-watchdog"; reg = <0x4000a000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; interrupts = <0 7>; status = "disabled"; }; spi1: spi@44004000 { compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; reg = <0x44004000 0x400>; #address-cells = <1>; #size-cells = <0>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x100>; interrupts = <35 5>; status = "disabled"; }; spi2: spi@4000b000 { compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; reg = <0x4000b000 0x400>; #address-cells = <1>; #size-cells = <0>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x800>; interrupts = <36 5>; status = "disabled"; }; spi3: spi@4000c000 { compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; reg = <0x4000c000 0x400>; #address-cells = <1>; #size-cells = <0>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x1000>; interrupts = <51 5>; status = "disabled"; }; spi4: spi@44005000 { compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; reg = <0x44005000 0x400>; #address-cells = <1>; #size-cells = <0>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x200>; interrupts = <84 5>; status = "disabled"; }; spi5: spi@44009000 { compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi"; reg = <0x44009000 0x400>; #address-cells = <1>; #size-cells = <0>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x400>; interrupts = <85 5>; status = "disabled"; }; usart2: serial@4000e000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x4000e000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; interrupts = <38 0>; status = "disabled"; }; usart3: serial@4000f000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x4000f000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; interrupts = <39 0>; status = "disabled"; }; uart4: serial@40010000 { compatible = "st,stm32-uart"; reg = <0x40010000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00010000>; interrupts = <52 0>; status = "disabled"; }; uart5: serial@40011000 { compatible = "st,stm32-uart"; reg = <0x40011000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; interrupts = <53 0>; status = "disabled"; }; usart6: serial@44003000 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x44003000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; interrupts = <71 0>; status = "disabled"; }; uart7: serial@40018000 { compatible = "st,stm32-uart"; reg = <0x40018000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; interrupts = <82 0>; status = "disabled"; }; uart8: serial@40019000 { compatible = "st,stm32-uart"; reg = <0x40019000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; interrupts = <83 0>; status = "disabled"; }; i2c5: i2c@40015000 { compatible = "st,stm32-i2c-v2"; clock-frequency = <I2C_BITRATE_STANDARD>; reg = <0x40015000 0x400>; #address-cells = <1>; #size-cells = <0>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>; interrupt-names = "event", "error"; interrupts = <107 0>, <108 0>; status = "disabled"; }; mailbox: mailbox@4c001000 { compatible = "st,stm32-ipcc-mailbox"; reg = <0x4c001000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>; interrupts = <103 0>, <104 0>; interrupt-names = "rxo", "txf"; status = "disabled"; }; ltdc: display-controller@5a001000 { compatible = "st,stm32-ltdc"; reg = <0x5a001000 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_er"; clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000001>; status = "disabled"; }; }; }; &nvic { arm,num-irq-priority-bits = <4>; }; |