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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 | /* * Copyright (c) 2020, NXP * * SPDX-License-Identifier: Apache-2.0 */ #include <mem.h> #include <arm/armv8-m.dtsi> #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h> #include <zephyr/dt-bindings/gpio/gpio.h> #include <zephyr/dt-bindings/i2c/i2c.h> / { chosen { zephyr,entropy = &trng; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-m33f"; reg = <0>; #address-cells = <1>; #size-cells = <1>; mpu: mpu@e000ed90 { compatible = "arm,armv8m-mpu"; reg = <0xe000ed90 0x40>; arm,num-mpu-regions = <8>; }; }; }; }; &sram { #address-cells = <1>; #size-cells = <1>; sram0: memory@20180000 { compatible = "mmio-sram"; reg = <0x20180000 DT_SIZE_K(3072)>; }; sram1: memory@40140000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x40140000 DT_SIZE_K(16)>; zephyr,memory-region = "SRAM1"; }; }; &systick { /* * RT600 relies by default on the OS Timer for system clock * implementation, so the SysTick node is not to be enabled. */ status = "disabled"; }; &peripheral { #address-cells = <1>; #size-cells = <1>; /* * Note that the offsets here are relative to the base address * defined in either nxp_rt6xx_ns.dtsi or nxp_rt6xx.dtsi. The base * addresses differ between non-secure (0x40000000) and secure * modes (0x50000000). */ clkctl0: clkctl@1000 { compatible = "nxp,lpc-syscon"; reg = <0x1000 0x1000>; #clock-cells = <1>; }; iocon: iocon@4000 { compatible = "nxp,lpc-iocon"; reg = <0x4000 0x1000>; pinctrl: pinctrl { compatible = "nxp,rt-iocon-pinctrl"; }; }; clkctl1: clkctl@21000 { compatible = "nxp,lpc-syscon"; reg = <0x21000 0x1000>; #clock-cells = <1>; }; uuid: uuid@2f50 { compatible = "nxp,lpc-uid"; reg = <0x2f50 0x10>; }; gpio0: gpio@0 { compatible = "nxp,lpc-gpio"; reg = <0x100000 0x1000>; interrupts = <4 2>,<5 2>,<6 2>,<7 2>; gpio-controller; #gpio-cells = <2>; port = <0>; }; gpio1: gpio@1 { compatible = "nxp,lpc-gpio"; reg = <0x100000 0x1000>; interrupts = <35 2>,<36 2>,<37 2>,<38 2>; gpio-controller; #gpio-cells = <2>; port = <1>; }; gpio2: gpio@2 { compatible = "nxp,lpc-gpio"; reg = <0x100000 0x1000>; gpio-controller; #gpio-cells = <2>; port = <2>; }; gpio3: gpio@3 { compatible = "nxp,lpc-gpio"; reg = <0x100000 0x1000>; gpio-controller; #gpio-cells = <2>; port = <3>; }; gpio4: gpio@4 { compatible = "nxp,lpc-gpio"; reg = <0x100000 0x1000>; gpio-controller; #gpio-cells = <2>; port = <4>; }; gpio7: gpio@7 { compatible = "nxp,lpc-gpio"; reg = <0x100000 0x1000>; gpio-controller; #gpio-cells = <2>; port = <7>; }; flexcomm0: flexcomm@106000 { compatible = "nxp,lpc-flexcomm"; reg = <0x106000 0x1000>; interrupts = <14 0>; clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>; status = "disabled"; }; flexcomm1: flexcomm@107000 { compatible = "nxp,lpc-flexcomm"; reg = <0x107000 0x1000>; interrupts = <15 0>; clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>; status = "disabled"; }; flexcomm2: flexcomm@108000 { compatible = "nxp,lpc-flexcomm"; reg = <0x108000 0x1000>; interrupts = <16 0>; clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>; status = "disabled"; }; flexcomm3: flexcomm@109000 { compatible = "nxp,lpc-flexcomm"; reg = <0x109000 0x1000>; interrupts = <17 0>; clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>; status = "disabled"; }; flexcomm4: flexcomm@122000 { compatible = "nxp,lpc-flexcomm"; reg = <0x122000 0x1000>; interrupts = <18 0>; clocks = <&clkctl1 MCUX_FLEXCOMM4_CLK>; status = "disabled"; }; flexcomm5: flexcomm@123000 { compatible = "nxp,lpc-flexcomm"; reg = <0x123000 0x1000>; interrupts = <19 0>; clocks = <&clkctl1 MCUX_FLEXCOMM5_CLK>; status = "disabled"; }; flexcomm6: flexcomm@124000 { compatible = "nxp,lpc-flexcomm"; reg = <0x124000 0x1000>; interrupts = <43 0>; clocks = <&clkctl1 MCUX_FLEXCOMM6_CLK>; status = "disabled"; }; flexcomm7: flexcomm@125000 { compatible = "nxp,lpc-flexcomm"; reg = <0x125000 0x1000>; interrupts = <44 0>; clocks = <&clkctl1 MCUX_FLEXCOMM7_CLK>; status = "disabled"; }; pmic_i2c: i2c@127000 { compatible = "nxp,lpc-i2c"; reg = <0x127000 0x1000>; interrupts = <21 0>; clocks = <&clkctl1 MCUX_PMIC_I2C_CLK>; status = "disabled"; }; usbhs: usbhs@144000 { compatible = "nxp,mcux-usbd"; reg = <0x144000 0x1000>; interrupts = <50 1>; num-bidir-endpoints = <6>; usb-controller-index = "LpcIp3511Hs0"; status = "disabled"; }; hs_lspi: spi@126000 { compatible = "nxp,lpc-spi"; /* Enabling cs-gpios below will allow using GPIO CS, rather than Flexcomm SS */ /* cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, <&gpio1 15 GPIO_ACTIVE_LOW>, <&gpio1 16 GPIO_ACTIVE_LOW>, <&gpio1 17 GPIO_ACTIVE_LOW>; */ reg = <0x126000 0x1000>; interrupts = <20 0>; clocks = <&clkctl1 MCUX_HS_SPI_CLK>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; dma0: dma-controller@104000 { compatible = "nxp,lpc-dma"; reg = <0x104000 0x1000>; interrupts = <1 0>; status = "disabled"; #dma-cells = <1>; }; dma1: dma-controller@105000 { compatible = "nxp,lpc-dma"; reg = <0x105000 0x1000>; interrupts = <54 0>; status = "disabled"; #dma-cells = <1>; }; os_timer: timers@113000 { compatible = "nxp,os-timer"; reg = <0x113000 0x1000>; interrupts = <41 0>; status = "disabled"; }; rtc: rtc@30000 { compatible = "nxp,lpc-rtc"; reg = <0x30000 0x1000>; interrupts = <32 0>; status = "disabled"; }; trng: random@138000 { compatible = "nxp,kinetis-trng"; reg = <0x138000 0x1000>; status = "okay"; interrupts = <31 0>; }; sc_timer: pwm@146000 { compatible = "nxp,sctimer-pwm"; reg = <0x146000 0x1000>; interrupts = <12 0>; status = "disabled"; prescaler = <8>; #pwm-cells = <3>; }; wwdt0: watchdog@e000 { compatible = "nxp,lpc-wwdt"; reg = <0xe000 0x1000>; interrupts = <0 0>; status = "disabled"; clk-divider = <1>; }; wwdt1: watchdog@2e000 { compatible = "nxp,lpc-wwdt"; reg = <0x2e000 0x1000>; interrupts = <52 0>; status = "disabled"; clk-divider = <1>; }; usdhc0: usdhc@136000 { compatible = "nxp,imx-usdhc"; reg = <0x136000 0x1000>; status = "disabled"; interrupts = <45 0>; clocks = <&clkctl1 MCUX_USDHC1_CLK>; max-current-330 = <1020>; max-current-180 = <1020>; max-bus-freq = <208000000>; min-bus-freq = <400000>; }; usdhc1: usdhc@137000 { compatible = "nxp,imx-usdhc"; reg = <0x137000 0x1000>; status = "disabled"; interrupts = <46 0>; clocks = <&clkctl1 MCUX_USDHC2_CLK>; max-current-330 = <1020>; max-current-180 = <1020>; max-bus-freq = <208000000>; min-bus-freq = <400000>; }; lpadc0: lpadc@13A0000 { compatible = "nxp,lpc-lpadc"; reg = <0x13A000 0x304>; interrupts = <22 0>; status = "disabled"; clk-divider = <1>; clk-source = <0>; voltage-ref= <2>; calibration-average = <128>; power-level = <1>; offset-value-a = <10>; offset-value-b = <10>; #io-channel-cells = <1>; }; ctimer0: ctimer@28000 { compatible = "nxp,lpc-ctimer"; reg = <0x28000 0x1000>; interrupts = <10 0>; status = "disabled"; clk-source = <1>; clocks = <&clkctl1 MCUX_CTIMER0_CLK>; mode = <0>; input = <0>; prescale = <0>; }; ctimer1: ctimer@29000 { compatible = "nxp,lpc-ctimer"; reg = <0x29000 0x1000>; interrupts = <11 0>; status = "disabled"; clk-source = <1>; clocks = <&clkctl1 MCUX_CTIMER1_CLK>; mode = <0>; input = <0>; prescale = <0>; }; ctimer2: ctimer@2a000 { compatible = "nxp,lpc-ctimer"; reg = <0x2a000 0x1000>; interrupts = <39 0>; status = "disabled"; clk-source = <1>; clocks = <&clkctl1 MCUX_CTIMER2_CLK>; mode = <0>; input = <0>; prescale = <0>; }; ctimer3: ctimer@2b000 { compatible = "nxp,lpc-ctimer"; reg = <0x2b000 0x1000>; interrupts = <13 0>; status = "disabled"; clk-source = <1>; clocks = <&clkctl1 MCUX_CTIMER3_CLK>; mode = <0>; input = <0>; prescale = <0>; }; ctimer4: ctimer@2c000 { compatible = "nxp,lpc-ctimer"; reg = <0x2c000 0x1000>; interrupts = <40 0>; status = "disabled"; clk-source = <1>; clocks = <&clkctl1 MCUX_CTIMER4_CLK>; mode = <0>; input = <0>; prescale = <0>; }; i3c0: i3c@36000 { compatible = "nxp,mcux-i3c"; reg = <0x36000 0x1000>; interrupts = <49 0>; clocks = <&clkctl1 MCUX_I3C_CLK>; clk-divider = <2>; clk-divider-slow = <1>; clk-divider-tc = <1>; status = "disabled"; #address-cells = <3>; #size-cells = <0>; }; }; &flexspi { compatible = "nxp,imx-flexspi"; interrupts = <42 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; &nvic { arm,num-irq-priority-bits = <3>; }; |