/*
 * Copyright 2022, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>

/ {
	chosen {
		zephyr,entropy = &trng;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-m33f";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv8m-mpu";
				reg = <0xe000ed90 0x40>;
				arm,num-mpu-regions = <8>;
			};
		};
	};
};

&sram {
	#address-cells = <1>;
	#size-cells = <1>;

	sram0: memory@20180000 {
		compatible = "mmio-sram";
		reg = <0x20180000 DT_SIZE_K(3072)>;
	};

	sram1: memory@40140000 {
		compatible =  "zephyr,memory-region", "mmio-sram";
		reg = <0x40140000 DT_SIZE_K(16)>;
		zephyr,memory-region = "SRAM1";
	};
};

&systick {
	/*
	 * RT500 relies by default on the OS Timer for system clock
	 * implementation, so the SysTick node is not to be enabled.
	 */
	status = "disabled";
};

&peripheral {
	#address-cells = <1>;
	#size-cells = <1>;
	/*
	 * Note that the offsets here are relative to the base address
	 * defined in either nxp_rt5xx_ns.dtsi or nxp_rt5xx.dtsi. The base
	 * addresses differ between non-secure (0x40000000) and secure
	 * modes (0x50000000).
	 */

	clkctl0: clkctl@1000 {
		compatible = "nxp,lpc-syscon";
		reg = <0x1000 0x1000>;
		#clock-cells = <1>;
	};

	iocon: iocon@4000 {
		compatible = "nxp,lpc-iocon";
		reg = <0x4000 0x1000>;
		pinctrl: pinctrl {
			compatible = "nxp,rt-iocon-pinctrl";
		};
	};

	clkctl1: clkctl@21000 {
		compatible = "nxp,lpc-syscon";
		reg = <0x21000 0x1000>;
		#clock-cells = <1>;
	};

	uuid: uuid@2f50 {
		compatible = "nxp,lpc-uid";
		reg = <0x2f50 0x10>;
	};

	gpio0: gpio@0 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x1000>;
		interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <0>;
	};

	gpio1: gpio@1 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x1000>;
		interrupts = <35 2>,<36 2>,<37 2>,<38 2>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <1>;
	};

	gpio2: gpio@2 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <2>;
	};

	gpio3: gpio@3 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <3>;
	};

	gpio4: gpio@4 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <4>;
	};

	gpio5: gpio@5 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <5>;
	};

	gpio6: gpio@6 {
		compatible = "nxp,lpc-gpio";
		reg = <0x100000 0x1000>;
		gpio-controller;
		#gpio-cells = <2>;
		port = <6>;
	};

	flexcomm0: flexcomm@106000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x106000 0x1000>;
		interrupts = <14 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM0_CLK>;
		status = "disabled";
	};

	flexcomm1: flexcomm@107000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x107000 0x1000>;
		interrupts = <15 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM1_CLK>;
		status = "disabled";
	};

	flexcomm2: flexcomm@108000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x108000 0x1000>;
		interrupts = <16 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM2_CLK>;
		status = "disabled";
	};

	flexcomm3: flexcomm@109000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x109000 0x1000>;
		interrupts = <17 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM3_CLK>;
		status = "disabled";
	};

	flexcomm4: flexcomm@122000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x122000 0x1000>;
		interrupts = <18 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM4_CLK>;
		status = "disabled";
	};

	flexcomm5: flexcomm@123000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x123000 0x1000>;
		interrupts = <19 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM5_CLK>;
		status = "disabled";
	};

	flexcomm6: flexcomm@124000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x124000 0x1000>;
		interrupts = <43 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM6_CLK>;
		status = "disabled";
	};

	flexcomm7: flexcomm@125000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x125000 0x1000>;
		interrupts = <44 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM7_CLK>;
		status = "disabled";
	};

	pmic_i2c: i2c@127000 {
		compatible = "nxp,lpc-i2c";
		reg = <0x127000 0x1000>;
		interrupts = <21 0>;
		clocks = <&clkctl1 MCUX_PMIC_I2C_CLK>;
		status = "disabled";
	};

	flexcomm8: flexcomm@209000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x209000 0x1000>;
		interrupts = <60 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM8_CLK>;
		status = "disabled";
	};

	flexcomm9: flexcomm@20a000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x20a000 0x1000>;
		interrupts = <61 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM9_CLK>;
		status = "disabled";
	};

	flexcomm10: flexcomm@20b000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x20b000 0x1000>;
		interrupts = <62 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM10_CLK>;
		status = "disabled";
	};

	flexcomm11: flexcomm@20c000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x20c000 0x1000>;
		interrupts = <63 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM11_CLK>;
		status = "disabled";
	};

	flexcomm12: flexcomm@20d000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x20d000 0x1000>;
		interrupts = <64 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM12_CLK>;
		status = "disabled";
	};

	flexcomm13: flexcomm@20e000 {
		compatible = "nxp,lpc-flexcomm";
		reg = <0x20e000 0x1000>;
		interrupts = <65 0>;
		clocks = <&clkctl1 MCUX_FLEXCOMM13_CLK>;
		status = "disabled";
	};

	usbhs: usbhs@144000 {
		compatible = "nxp,mcux-usbd";
		reg = <0x144000 0x1000>;
		interrupts = <50 1>;
		num-bidir-endpoints = <6>;
		usb-controller-index = "LpcIp3511Hs0";
		status = "disabled";
	};

	hs_lspi: spi@126000 {
		compatible = "nxp,lpc-spi";
		reg = <0x126000 0x1000>;
		interrupts = <20 0>;
		clocks = <&clkctl1 MCUX_HS_SPI_CLK>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	hs_lspi1: spi@128000 {
		compatible = "nxp,lpc-spi";
		reg = <0x128000 0x1000>;
		interrupts = <66 0>;
		clocks = <&clkctl1 MCUX_HS_SPI1_CLK>;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <0>;
	};

	dma0: dma-controller@104000 {
		compatible = "nxp,lpc-dma";
		reg = <0x104000 0x1000>;
		interrupts = <1 0>;
		status = "disabled";
		#dma-cells = <1>;
	};

	dma1: dma-controller@105000 {
		compatible = "nxp,lpc-dma";
		reg = <0x105000 0x1000>;
		interrupts = <54 0>;
		status = "disabled";
		#dma-cells = <1>;
	};

	os_timer: timers@113000 {
		compatible = "nxp,os-timer";
		reg = <0x113000 0x1000>;
		interrupts = <41 0>;
		status = "disabled";
	};

	rtc: rtc@30000 {
		compatible = "nxp,lpc-rtc";
		reg = <0x30000 0x1000>;
		interrupts = <32 0>;
		status = "disabled";
	};

	trng: random@138000 {
		compatible = "nxp,kinetis-trng";
		reg = <0x138000 0x1000>;
		status = "okay";
		interrupts = <31 0>;
	};

	sc_timer: pwm@146000 {
		compatible = "nxp,sctimer-pwm";
		reg = <0x146000 0x1000>;
		interrupts = <12 0>;
		status = "disabled";
		prescaler = <8>;
		#pwm-cells = <3>;
	};

	wwdt0: watchdog@e000 {
		compatible = "nxp,lpc-wwdt";
		reg = <0xe000 0x1000>;
		interrupts = <0 0>;
		status = "disabled";
		clk-divider = <1>;
	};

	wwdt1: watchdog@2e000 {
		compatible = "nxp,lpc-wwdt";
		reg = <0x2e000 0x1000>;
		interrupts = <52 0>;
		status = "disabled";
		clk-divider = <1>;
	};

	usdhc1: usdhc@136000 {
		compatible = "nxp,imx-usdhc";
		reg = <0x136000 0x1000>;
		status = "disabled";
		interrupts = <45 0>;
		clocks = <&clkctl1 MCUX_USDHC1_CLK>;
		max-current-330 = <1020>;
		max-current-180 = <1020>;
		max-bus-freq = <208000000>;
		min-bus-freq = <400000>;
	};

	usdhc2: usdhc@137000 {
		compatible = "nxp,imx-usdhc";
		reg = <0x137000 0x1000>;
		status = "disabled";
		interrupts = <46 0>;
		clocks = <&clkctl1 MCUX_USDHC2_CLK>;
		max-current-330 = <1020>;
		max-current-180 = <1020>;
		max-bus-freq = <208000000>;
		min-bus-freq = <400000>;
	};

	lpadc0: lpadc@13A0000 {
		compatible = "nxp,lpc-lpadc";
		reg = <0x13A000 0x304>;
		interrupts = <22 0>;
		status = "disabled";
		clk-divider = <1>;
		clk-source = <0>;
		voltage-ref= <2>;
		calibration-average = <128>;
		power-level = <1>;
		offset-value-a = <10>;
		offset-value-b = <10>;
		#io-channel-cells = <1>;
	};

	ctimer0: ctimer@28000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x28000 0x1000>;
		interrupts = <10 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER0_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer1: ctimer@29000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x29000 0x1000>;
		interrupts = <11 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER1_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer2: ctimer@2a000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x2a000 0x1000>;
		interrupts = <39 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER2_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer3: ctimer@2b000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x2b000 0x1000>;
		interrupts = <13 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER3_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};

	ctimer4: ctimer@2c000 {
		compatible = "nxp,lpc-ctimer";
		reg = <0x2c000 0x1000>;
		interrupts = <40 0>;
		status = "disabled";
		clk-source = <1>;
		clocks = <&clkctl1 MCUX_CTIMER4_CLK>;
		mode = <0>;
		input = <0>;
		prescale = <0>;
	};
};

&flexspi {
	compatible = "nxp,imx-flexspi";
	status = "disabled";
	interrupts = <42 0>;
	#address-cells = <1>;
	#size-cells = <0>;
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};