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Defined in 2 files as a prototype:
- include/zephyr/arch/arm/aarch32/exc.h, line 65 (as a prototype)
- include/zephyr/arch/arm/aarch32/irq.h, line 28 (as a prototype)
Defined in 3 files as a macro:
- include/zephyr/toolchain/gcc.h, line 316 (as a macro)
- include/zephyr/toolchain/gcc.h, line 341 (as a macro)
- include/zephyr/toolchain/mwdt.h, line 58 (as a macro)
Referenced in 91 files:
- arch/arc/core/cpu_idle.S
- arch/arc/core/fast_irq.S
- arch/arc/core/fault_s.S
- arch/arc/core/isr_wrapper.S
- arch/arc/core/regular_irq.S
- arch/arc/core/reset.S
- arch/arc/core/secureshield/arc_secure.S
- arch/arc/core/switch.S, line 26
- arch/arc/core/thread_entry_wrapper.S
- arch/arc/core/userspace.S
- arch/arc/include/vector_table.h
- arch/arm/core/aarch32/cortex_a_r/__aeabi_read_tp.S, line 11
- arch/arm/core/aarch32/cortex_a_r/exc.S
- arch/arm/core/aarch32/cortex_a_r/exc_exit.S
- arch/arm/core/aarch32/cortex_a_r/reset.S
- arch/arm/core/aarch32/cortex_a_r/vector_table.h
- arch/arm/core/aarch32/cortex_m/__aeabi_read_tp.S, line 11
- arch/arm/core/aarch32/cortex_m/exc_exit.S
- arch/arm/core/aarch32/cortex_m/fault_s.S
- arch/arm/core/aarch32/cortex_m/reset.S
- arch/arm/core/aarch32/cortex_m/vector_table.h
- arch/arm/core/aarch32/cpu_idle.S
- arch/arm/core/aarch32/irq_relay.S, line 50
- arch/arm/core/aarch32/isr_wrapper.S
- arch/arm/core/aarch32/nmi_on_reset.S, line 23
- arch/arm/core/aarch32/swap_helper.S
- arch/arm/core/aarch32/userspace.S
- arch/arm64/core/cpu_idle.S
- arch/arm64/core/fpu.S
- arch/arm64/core/isr_wrapper.S
- arch/arm64/core/mmu.S, line 17
- arch/arm64/core/reset.S
- arch/arm64/core/smccc-call.S
- arch/arm64/core/switch.S
- arch/arm64/core/userspace.S
- arch/arm64/core/vector_table.S
- arch/arm64/core/xen/hypercall.S, line 13
- arch/mips/core/isr.S
- arch/mips/core/reset.S
- arch/mips/core/swap.S, line 21
- arch/nios2/core/crt0.S
- arch/nios2/core/exception.S
- arch/nios2/core/reset.S, line 9
- arch/nios2/core/swap.S
- arch/riscv/core/isr.S
- arch/riscv/core/pmp.S, line 36
- arch/riscv/core/reset.S
- arch/riscv/core/switch.S
- arch/riscv/core/userspace.S
- arch/sparc/core/fault_trap.S
- arch/sparc/core/interrupt_trap.S
- arch/sparc/core/reset_trap.S
- arch/sparc/core/sw_trap_set_pil.S, line 11
- arch/sparc/core/switch.S
- arch/sparc/core/trap_table_mvt.S
- arch/sparc/core/window_trap.S
- arch/x86/core/ia32/crt0.S
- arch/x86/core/ia32/excstub.S
- arch/x86/core/ia32/intstub.S
- arch/x86/core/ia32/swap.S
- arch/x86/core/ia32/userspace.S
- drivers/interrupt_controller/intc_loapic_spurious.S, line 15
- include/zephyr/arch/arm/aarch32/irq.h
- include/zephyr/arch/arm64/irq.h
- include/zephyr/arch/x86/ia32/asm.h
- include/zephyr/toolchain/gcc.h, line 346
- soc/arm/nordic_nrf/common/soc_nrf_common.S
- soc/arm/nxp_kinetis/k2x/wdog.S, line 20
- soc/arm/nxp_kinetis/k6x/wdog.S, line 20
- soc/arm/nxp_kinetis/k8x/wdog.S, line 20
- soc/arm/nxp_kinetis/kv5x/wdog.S, line 20
- soc/arm/nxp_kinetis/kwx/wdog.S, line 20
- soc/arm/nxp_lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S, line 29
- soc/arm/ti_lm3s6965/reboot.S
- soc/mips/qemu_malta/vector.S
- soc/riscv/esp32c3/soc_irq.S
- soc/riscv/esp32c3/vectors.S, line 13
- soc/riscv/openisa_rv32m1/soc_irq.S
- soc/riscv/openisa_rv32m1/vector.S
- soc/riscv/openisa_rv32m1/wdog.S, line 12
- soc/riscv/riscv-ite/common/soc_irq.S, line 18
- soc/riscv/riscv-ite/common/vector.S
- soc/riscv/riscv-privilege/andes_v5/soc_irq.S
- soc/riscv/riscv-privilege/andes_v5/start.S, line 11
- soc/riscv/riscv-privilege/common/vector.S
- soc/riscv/riscv-privilege/gd32vf103/entry.S, line 11
- soc/riscv/riscv-privilege/neorv32/reset.S
- soc/riscv/riscv-privilege/neorv32/soc_irq.S, line 9
- soc/riscv/riscv-privilege/telink_b91/soc_irq.S
- soc/riscv/riscv-privilege/telink_b91/start.S, line 17
- tests/arch/x86/static_idt/src/test_stubs.S