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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 | /* SPDX-License-Identifier: Apache-2.0 */ #include <xtensa/xtensa.dtsi> #include <zephyr/dt-bindings/i2c/i2c.h> #include <zephyr/dt-bindings/gpio/gpio.h> #include <mem.h> #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx6"; reg = <0>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx6"; reg = <1>; }; }; sram0: memory@be000000 { compatible = "mmio-sram"; reg = <0xbe000000 DT_SIZE_M(4)>; }; sram1: memory@be800000 { compatible = "mmio-sram"; reg = <0xbe800000 DT_SIZE_K(64)>; }; sysclk: system-clock { compatible = "fixed-clock"; clock-frequency = <400000000>; #clock-cells = <0>; }; soc { core_intc: core_intc@0 { compatible = "cdns,xtensa-core-intc"; reg = <0x00 0x400>; interrupt-controller; #interrupt-cells = <3>; }; shim: shim@71f00 { compatible = "intel,cavs-shim"; reg = <0x71f00 0x100>; }; cavs0: cavs@78800 { compatible = "intel,cavs-intc"; reg = <0x78800 0x10>; interrupt-controller; #interrupt-cells = <3>; interrupts = <6 0 0>; interrupt-parent = <&core_intc>; label = "CAVS_0"; }; cavs1: cavs@78810 { compatible = "intel,cavs-intc"; reg = <0x78810 0x10>; interrupt-controller; #interrupt-cells = <3>; interrupts = <0xA 0 0>; interrupt-parent = <&core_intc>; label = "CAVS_1"; }; cavs2: cavs@78820 { compatible = "intel,cavs-intc"; reg = <0x78820 0x10>; interrupt-controller; #interrupt-cells = <3>; interrupts = <0XD 0 0>; interrupt-parent = <&core_intc>; label = "CAVS_2"; }; cavs3: cavs@78830 { compatible = "intel,cavs-intc"; reg = <0x78830 0x10>; interrupt-controller; #interrupt-cells = <3>; interrupts = <0x10 0 0>; interrupt-parent = <&core_intc>; label = "CAVS_3"; }; idc: idc@1200 { compatible = "intel,cavs-idc"; label = "CAVS_IDC"; reg = <0x1200 0x80>; interrupts = <8 0 0>; interrupt-parent = <&cavs0>; }; dw_intc: intc@81800 { compatible = "snps,designware-intc"; reg = <0x00081800 0x400>; interrupt-controller; #interrupt-cells = <3>; interrupts = <6 0 0>; num-irqs = <9>; interrupt-parent = <&cavs0>; label = "DW_INTC"; }; gpio0: gpio@80c00 { compatible = "snps,designware-gpio"; reg = <0x00080c00 0x400>; ngpios = <32>; label = "GPIO"; interrupts = <3 1 0>; interrupt-parent = <&dw_intc>; gpio-controller; #gpio-cells = <2>; }; pinmux: pinmux@81c30 { compatible = "intel,s1000-pinmux"; reg = <0x00081c30 0xC>; }; uart0: uart@80800 { compatible = "ns16550"; reg = <0x80800 0x400>; label = "UART_0"; clock-frequency = <38400000>; interrupts = <2 0 0>; interrupt-parent = <&dw_intc>; status = "disabled"; }; i2c0: i2c@80400 { compatible = "snps,designware-i2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x80400 0x400>; interrupts = <1 0 0>; interrupt-parent = <&dw_intc>; label = "I2C_0"; status = "disabled"; }; spi0: spi@e000 { compatible = "snps,designware-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0000E000 0x400>; clocks = <&sysclk>; interrupts = <6 0 0>; interrupt-parent = <&dw_intc>; label = "SPI_0"; }; dma0: dma@7c000 { compatible = "snps,designware-dma"; #dma-cells = <1>; reg = <0x0007C000 0x1000>; interrupts = <0x10 0 0>; interrupt-parent = <&cavs3>; label = "DMA_0"; status = "okay"; }; dma1: dma@7d000 { compatible = "snps,designware-dma"; #dma-cells = <1>; reg = <0x0007D000 0x1000>; interrupts = <0x00 0 0>; interrupt-parent = <&cavs1>; label = "DMA_1"; status = "disabled"; }; dma2: dma@7e000 { compatible = "snps,designware-dma"; #dma-cells = <1>; reg = <0x0007E000 0x1000>; interrupts = <0x00 0 0>; interrupt-parent = <&cavs2>; label = "DMA_2"; status = "disabled"; }; usb: usb@a0000 { compatible = "snps,designware-usb"; reg = <0x000A0000 0x1000>; interrupts = <0x07 IRQ_TYPE_LOWEST_EDGE_RISING 3>; interrupt-parent = <&cavs0>; num-bidir-endpoints = <6>; label = "USB_0"; status = "disabled"; }; i2s1: i2s@77200 { compatible = "intel,cavs-i2s"; #address-cells = <1>; #size-cells = <0>; reg = <0x00077200 0x200 0x00078D08 0x008>; interrupts = <0x01 0 0>; interrupt-parent = <&cavs3>; dmas = <&dma0 2 &dma0 3>; dma-names = "tx", "rx"; label = "I2S_1"; status = "okay"; }; i2s2: i2s@77400 { compatible = "intel,cavs-i2s"; #address-cells = <1>; #size-cells = <0>; reg = <0x00077400 0x200 0x00078D10 0x008>; interrupts = <0x02 0 0>; interrupt-parent = <&cavs3>; dmas = <&dma0 4 &dma0 5>; dma-names = "tx", "rx"; label = "I2S_2"; status = "okay"; }; i2s3: i2s@77600 { compatible = "intel,cavs-i2s"; #address-cells = <1>; #size-cells = <0>; reg = <0x00077600 0x200 0x00078D18 0x008>; interrupts = <0x03 0 0>; interrupt-parent = <&cavs3>; dmas = <&dma0 6 &dma0 7>; dma-names = "tx", "rx"; label = "I2S_3"; status = "okay"; }; gna: gna@e800 { compatible = "intel,gna"; reg = <0x0000E800 0x100>; interrupt-controller; interrupts = <5 0 0>; interrupt-parent = <&cavs0>; label = "GNA0"; }; }; }; |