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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 | /* * Copyright (c) 2019,2022 Intel Corporation * * SPDX-License-Identifier: Apache-2.0 */ #include <xtensa/intel/intel_cavs.dtsi> #include <mem.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx6"; reg = <0>; }; cpu1: cpu@1 { device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx6"; reg = <1>; }; }; sram0: memory@be000000 { device_type = "memory"; compatible = "mmio-sram"; reg = <0xbe000000 DT_SIZE_K(1920)>; }; sram1: memory@be800000 { device_type = "memory"; compatible = "mmio-sram"; reg = <0xbe800000 DT_SIZE_K(64)>; }; soc { shim: shim@71f00 { compatible = "intel,cavs-shim"; reg = <0x71f00 0x100>; }; win: win@71a00 { compatible = "intel,cavs-win"; reg = <0x71a00 0x20>; }; l2lm: l2lm@71d00 { compatible = "intel,cavs-l2lm"; reg = <0x71d00 0x20>; }; core_intc: core_intc@0 { compatible = "cdns,xtensa-core-intc"; reg = <0x00 0x400>; interrupt-controller; #interrupt-cells = <3>; }; cavs0: cavs@78800 { compatible = "intel,cavs-intc"; reg = <0x78800 0x10>; interrupt-controller; #interrupt-cells = <3>; interrupts = <6 0 0>; interrupt-parent = <&core_intc>; label = "CAVS_0"; }; cavs1: cavs@78810 { compatible = "intel,cavs-intc"; reg = <0x78810 0x10>; interrupt-controller; #interrupt-cells = <3>; interrupts = <0xA 0 0>; interrupt-parent = <&core_intc>; label = "CAVS_1"; }; cavs2: cavs@78820 { compatible = "intel,cavs-intc"; reg = <0x78820 0x10>; interrupt-controller; #interrupt-cells = <3>; interrupts = <0XD 0 0>; interrupt-parent = <&core_intc>; label = "CAVS_2"; }; cavs3: cavs@78830 { compatible = "intel,cavs-intc"; reg = <0x78830 0x10>; interrupt-controller; #interrupt-cells = <3>; interrupts = <0x10 0 0>; interrupt-parent = <&core_intc>; label = "CAVS_3"; }; idc: idc@1200 { compatible = "intel,cavs-idc"; label = "CAVS_IDC"; reg = <0x1200 0x80>; interrupts = <8 0 0>; interrupt-parent = <&cavs0>; }; tlb: tlb@3000 { compatible = "intel,adsp-tlb"; reg = <0x3000 0x1000>; }; }; }; |