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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 | /* * Copyright (c) 2019 Lexmark International, Inc. * * SPDX-License-Identifier: Apache-2.0 */ #include <mem.h> #include <arm/armv7-r.dtsi> #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h> #include <zephyr/dt-bindings/ethernet/xlnx_gem.h> / { soc { flash0: flash@c0000000 { compatible = "soc-nv-flash"; reg = <0xc0000000 DT_SIZE_M(32)>; }; sram0: memory@0 { compatible = "mmio-sram"; reg = <0 DT_SIZE_M(64)>; }; ocm: memory@fffc0000 { compatible = "zephyr,memory-region", "xlnx,zynq-ocm"; reg = <0xfffc0000 DT_SIZE_K(256)>; zephyr,memory-region = "OCM"; }; uart0: uart@ff000000 { compatible = "xlnx,xuartps"; reg = <0xff000000 0x4c>; status = "disabled"; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; label = "UART_0"; }; uart1: uart@ff010000 { compatible = "xlnx,xuartps"; reg = <0xff010000 0x4c>; status = "disabled"; interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; label = "UART_1"; }; ttc0: timer@ff110000 { compatible = "xlnx,ttcps"; status = "disabled"; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1", "irq_2"; reg = <0xff110000 0x1000>; label = "ttc0"; }; ttc1: timer@ff120000 { compatible = "xlnx,ttcps"; status = "disabled"; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 40 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1", "irq_2"; reg = <0xff120000 0x1000>; label = "ttc1"; }; ttc2: timer@ff130000 { compatible = "xlnx,ttcps"; status = "disabled"; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 44 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1", "irq_2"; reg = <0xff130000 0x1000>; label = "ttc2"; }; ttc3: timer@ff140000 { compatible = "xlnx,ttcps"; status = "disabled"; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 46 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 47 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1", "irq_2"; reg = <0xff140000 0x1000>; label = "ttc3"; }; gem0: ethernet@ff0b0000 { compatible = "xlnx,gem"; reg = <0xff0b0000 0x1000>, <0xff5e0050 0x4>; status = "disabled"; interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 58 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; label = "gem0"; mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; phy-poll-interval = <1000>; link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; hw-rx-buffer-offset = <0>; hw-tx-buffer-size-full; rx-buffer-descriptors = <32>; tx-buffer-descriptors = <32>; rx-buffer-size = <512>; tx-buffer-size = <512>; discard-rx-fcs; unicast-hash; full-duplex; }; gem1: ethernet@ff0c0000 { compatible = "xlnx,gem"; reg = <0xff0c0000 0x1000>, <0xff5e0054 0x4>; status = "disabled"; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 60 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; label = "gem1"; mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; phy-poll-interval = <1000>; link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; hw-rx-buffer-offset = <0>; hw-tx-buffer-size-full; rx-buffer-descriptors = <32>; tx-buffer-descriptors = <32>; rx-buffer-size = <512>; tx-buffer-size = <512>; discard-rx-fcs; unicast-hash; full-duplex; }; gem2: ethernet@ff0d0000 { compatible = "xlnx,gem"; reg = <0xff0d0000 0x1000>, <0xff5e0058 0x4>; status = "disabled"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 62 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; label = "gem2"; mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; phy-poll-interval = <1000>; link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; hw-rx-buffer-offset = <0>; hw-tx-buffer-size-full; rx-buffer-descriptors = <32>; tx-buffer-descriptors = <32>; rx-buffer-size = <512>; tx-buffer-size = <512>; discard-rx-fcs; unicast-hash; full-duplex; }; gem3: ethernet@ff0e0000 { compatible = "xlnx,gem"; reg = <0xff0e0000 0x1000>, <0xff5e005c 0x4>; status = "disabled"; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>, <GIC_SPI 64 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; label = "gem3"; mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>; phy-poll-interval = <1000>; link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>; amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>; amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>; hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>; hw-rx-buffer-offset = <0>; hw-tx-buffer-size-full; rx-buffer-descriptors = <32>; tx-buffer-descriptors = <32>; rx-buffer-size = <512>; tx-buffer-size = <512>; discard-rx-fcs; unicast-hash; full-duplex; }; psgpio: gpio@ff0a0000 { compatible = "xlnx,ps-gpio"; status = "disabled"; reg = <0xff0a0000 0x1000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; label = "psgpio"; ranges; #address-cells = <1>; #size-cells = <0>; psgpio_bank0: psgpio_bank@0 { compatible = "xlnx,ps-gpio-bank"; reg = <0x0>; label = "psgpio_bank0_mio"; gpio-controller; #gpio-cells = <2>; ngpios = <26>; status = "okay"; }; psgpio_bank1: psgpio_bank@1 { compatible = "xlnx,ps-gpio-bank"; reg = <0x1>; label = "psgpio_bank1_mio"; gpio-controller; #gpio-cells = <2>; ngpios = <26>; status = "okay"; }; psgpio_bank2: psgpio_bank@2 { compatible = "xlnx,ps-gpio-bank"; reg = <0x2>; label = "psgpio_bank2_mio"; gpio-controller; #gpio-cells = <2>; ngpios = <26>; status = "okay"; }; psgpio_bank3: psgpio_bank@3 { compatible = "xlnx,ps-gpio-bank"; reg = <0x3>; label = "psgpio_bank3_emio"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; status = "okay"; }; psgpio_bank4: psgpio_bank@4 { compatible = "xlnx,ps-gpio-bank"; reg = <0x4>; label = "psgpio_bank4_emio"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; status = "okay"; }; psgpio_bank5: psgpio_bank@5 { compatible = "xlnx,ps-gpio-bank"; reg = <0x5>; label = "psgpio_bank5_emio"; gpio-controller; #gpio-cells = <2>; ngpios = <32>; status = "okay"; }; }; }; }; |