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/* * Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com> * * SPDX-License-Identifier: Apache-2.0 */ #include <st/h7/stm32h7_dualcore.dtsi> #include <zephyr/dt-bindings/display/stm32_ltdc.h> / { soc { flash-controller@52002000 { flash0: flash@8000000 { compatible = "soc-nv-flash"; write-block-size = <32>; erase-block-size = <DT_SIZE_K(128)>; }; flash1: flash@8100000 { compatible = "soc-nv-flash"; write-block-size = <32>; erase-block-size = <DT_SIZE_K(128)>; }; }; dmamux1: dmamux@40020800 { dma-requests= <107>; }; ltdc: display-controller@50001000 { compatible = "st,stm32-ltdc"; reg = <0x50001000 0x200>; interrupts = <88 0>, <89 0>; interrupt-names = "ltdc", "ltdc_er"; clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>; label = "LTDC"; status = "disabled"; }; }; /* * The RAM memories placed here can be used by both cores M4/M7 * For more information see reference manual and datasheet to STM32H745 * (RM0399 Rev 3) */ /* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */ sram0: memory@24000000 { reg = <0x24000000 DT_SIZE_K(512)>; compatible = "mmio-sram"; }; /* System data RAM accessible over AHB bus: SRAM1 in D2 domain */ sram1: memory@30000000 { reg = <0x30000000 DT_SIZE_K(128)>; compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "SRAM1"; }; /* System data RAM accessible over AHB bus: SRAM2 in D2 domain */ sram2: memory@30020000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x30020000 DT_SIZE_K(128)>; zephyr,memory-region = "SRAM2"; }; /* System data RAM accessible over AHB bus: SRAM3 in D2 domain */ sram3: memory@30040000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x30040000 DT_SIZE_K(32)>; zephyr,memory-region = "SRAM3"; }; /* System data RAM accessible over AHB bus: SRAM4 in D3 domain */ sram4: memory@38000000 { reg = <0x38000000 DT_SIZE_K(64)>; compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "SRAM4"; }; }; |