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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 | /* SPDX-License-Identifier: Apache-2.0 */ #include <mem.h> #include "armv6-m.dtsi" #include <zephyr/dt-bindings/clock/kinetis_sim.h> #include <zephyr/dt-bindings/clock/kinetis_mcg.h> #include <zephyr/dt-bindings/gpio/gpio.h> #include <zephyr/dt-bindings/i2c/i2c.h> #include <zephyr/dt-bindings/pwm/pwm.h> / { chosen { zephyr,entropy = &trng; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m0+"; reg = <0>; }; }; sram0: memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 DT_SIZE_K(16)>; }; /* Dummy pinctrl node, filled with pin mux options at board level */ pinctrl: pinctrl { compatible = "nxp,kinetis-pinctrl"; status = "okay"; }; soc { mcg: clock-controller@40064000 { compatible = "nxp,kinetis-mcg"; reg = <0x40064000 0x13>; label = "MCG"; #clock-cells = <1>; }; osc: clock-controller@40065000 { compatible = "nxp,kw41z-osc"; reg = <0x40065000 0x4>; enable-external-reference; }; rtc: rtc@4003d000 { compatible = "nxp,kw41z-rtc"; reg = <0x4003d000 0x20>; clock-frequency = <32768>; }; sim: sim@40047000 { compatible = "nxp,kinetis-sim"; reg = <0x40047000 0x1060>; label = "SIM"; #clock-cells = <3>; core_clk { compatible = "fixed-factor-clock"; clocks = <&mcg KINETIS_MCG_OUT_CLK>; clock-div = <1>; #clock-cells = <0>; }; flash_clk { compatible = "fixed-factor-clock"; clocks = <&mcg KINETIS_MCG_OUT_CLK>; clock-div = <2>; #clock-cells = <0>; }; }; ftfa: flash-controller@40020000 { compatible = "nxp,kinetis-ftfa"; label = "FLASH_CTRL"; reg = <0x40020000 0x2c>; interrupts = <5 0>; #address-cells = <1>; #size-cells = <1>; flash0: flash@0 { compatible = "soc-nv-flash"; label = "MCUX_FLASH"; reg = <0 DT_SIZE_K(512)>; erase-block-size = <1024>; write-block-size = <4>; }; }; i2c0: i2c@40066000 { compatible = "nxp,kinetis-i2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40066000 0x1000>; interrupts = <8 0>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>; label = "I2C_0"; status = "disabled"; }; i2c1: i2c@40067000 { compatible = "nxp,kinetis-i2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40067000 0x1000>; interrupts = <9 0>; clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 7>; label = "I2C_1"; status = "disabled"; }; lpuart0: lpuart@40054000 { compatible = "nxp,kinetis-lpuart"; reg = <0x40054000 0x18>; interrupts = <12 0>; clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>; label = "UART_0"; status = "disabled"; }; porta: pinmux@40049000 { compatible = "nxp,kinetis-pinmux"; reg = <0x40049000 0xa4>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>; }; portb: pinmux@4004a000 { compatible = "nxp,kinetis-pinmux"; reg = <0x4004a000 0xa4>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>; }; portc: pinmux@4004b000 { compatible = "nxp,kinetis-pinmux"; reg = <0x4004b000 0xa4>; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>; }; gpioa: gpio@400ff000 { compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x400ff000 0x40>; interrupts = <30 2>; label = "GPIO_0"; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&porta>; }; gpiob: gpio@400ff040 { compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x400ff040 0x40>; label = "GPIO_2"; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portb>; }; gpioc: gpio@400ff080 { compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x400ff080 0x40>; interrupts = <31 2>; label = "GPIO_3"; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portc>; }; spi0: spi@4002c000 { compatible = "nxp,kinetis-dspi"; reg = <0x4002c000 0x9C>; interrupts = <10 3>; label = "SPI_0"; clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@4002d000 { compatible = "nxp,kinetis-dspi"; reg = <0x4002d000 0x9C>; interrupts = <29 3>; label = "SPI_1"; clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; tpm0: pwm@40038000 { compatible = "nxp,kw41z-pwm"; reg = <0x40038000 0x88>; prescaler = <2>; period = <1000>; /* channel information needed - fixme */ }; tpm1: pwm@40039000 { compatible = "nxp,kw41z-pwm"; reg = <0x40039000 0x88>; prescaler = <2>; period = <1000>; /* channel information needed - fixme */ }; tpm2: pwm@4003a000 { compatible = "nxp,kw41z-pwm"; reg = <0x4003a000 0x88>; prescaler = <2>; period = <1000>; /* channel information needed - fixme */ }; adc0: adc@4003b000{ compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; interrupts = <15 0>; label = "ADC_0"; status = "disabled"; #io-channel-cells = <1>; }; trng: random@40029000 { compatible = "nxp,kinetis-trng"; reg = <0x40029000 0x1000>; status = "okay"; interrupts = <13 0>; label = "TRNG"; }; }; }; &nvic { arm,num-irq-priority-bits = <2>; }; |