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/* * Copyright (c) 2019 SEAL AG * * SPDX-License-Identifier: Apache-2.0 */ #include <mem.h> #include <nxp/nxp_k8x.dtsi> / { /* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a * contiguous block in the memory map, however misaligned accesses * across the 0x2000_0000 boundary are not supported in the Arm * Cortex-M4 architecture. For clarity and to avoid the temptation for * someone to extend sram0 without solving this issue, we define two * separate memory nodes here and only use the upper one for now. A * potential solution has been proposed in binutils: * https://sourceware.org/ml/binutils/2017-02/msg00250.html */ sram_l: memory@1fff0000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x1fff0000 DT_SIZE_K(64)>; zephyr,memory-region = "SRAML"; }; sram0: memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 DT_SIZE_K(192)>; }; }; &ftfa { flash0: flash@0 { compatible = "soc-nv-flash"; label = "MCUX_FLASH"; reg = <0x0 DT_SIZE_K(256)>; erase-block-size = <DT_SIZE_K(4)>; write-block-size = <4>; }; }; |