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/*
* Copyright (c) 2018, Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
//#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#define DT_APB_CLK_HZ 100000000
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem";
reg = <0>;
};
intc: arcv2-intc {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
};
iccm0: iccm@60000000 {
compatible = "arc,iccm";
reg = <0x60000000 0x20000>;
};
dccm0: dccm@80000000 {
compatible = "arc,dccm";
reg = <0x80000000 0x20000>;
};
/* this is (Pseudo SRAM), so treat it like mmio-sram */
sram0: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000000>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart0: uart@f0004000 {
compatible = "ns16550";
clock-frequency = <DT_APB_CLK_HZ>;
reg = <0xf0004000 0x1000>;
label = "UART_0";
interrupt-parent = <&intc>;
};
gpio0: gpio@f0002000 {
compatible = "snps,designware-gpio";
reg = <0xf0002000 0xc>;
ngpios = <4>;
label = "GPIO_0";
interrupt-parent = <&intc>;
gpio-controller;
#gpio-cells = <2>;
};
gpio1: gpio@f000200c {
compatible = "snps,designware-gpio";
reg = <0xf000200c 0xc>;
ngpios = <8>;
label = "GPIO_1";
interrupt-parent = <&intc>;
interrupts = <0 1>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
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