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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 | /* * Copyright (c) 2021 Katsuhiro Suzuki * * SPDX-License-Identifier: Apache-2.0 */ #include <zephyr/dt-bindings/gpio/gpio.h> #include <freq.h> / { #address-cells = <1>; #size-cells = <1>; compatible = "sifive,FU540-C000", "fu540-dev", "sifive-dev"; model = "sifive,FU540"; clocks { coreclk: core-clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <DT_FREQ_M(1000)>; }; tlclk: tl-clk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&coreclk>; clock-div = <2>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu: cpu@0 { compatible = "riscv,sifive-e51"; device_type = "cpu"; reg = <0>; riscv,isa = "rv64imac"; status = "okay"; hlic: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; modeselect: rom@1000 { compatible = "sifive,modeselect0"; reg = <0x1000 0x1000>; reg-names = "mem"; }; maskrom: rom@10000 { compatible = "sifive,maskrom0"; reg = <0x10000 0x8000>; reg-names = "mem"; }; dtim: dtim@1000000 { compatible = "sifive,dtim0"; reg = <0x1000000 0x2000>; reg-names = "mem"; }; itim0: itim0@1800000 { compatible = "sifive,itim0"; reg = <0x1800000 0x2000>; reg-names = "mem"; }; itim1: itim1@1808000 { compatible = "sifive,itim0"; reg = <0x1808000 0x7000>; reg-names = "mem"; }; itim2: itim2@1810000 { compatible = "sifive,itim0"; reg = <0x1810000 0x7000>; reg-names = "mem"; }; itim3: itim3@1818000 { compatible = "sifive,itim0"; reg = <0x1818000 0x7000>; reg-names = "mem"; }; itim4: itim4@1820000 { compatible = "sifive,itim0"; reg = <0x1820000 0x7000>; reg-names = "mem"; }; clint: clint@2000000 { #interrupt-cells = <1>; compatible = "riscv,clint0"; interrupt-controller; interrupts-extended = <&hlic 3 &hlic 7>; reg = <0x2000000 0x10000>; reg-names = "control"; }; l2lim: l2lim@8000000 { compatible = "sifive,l2lim0"; reg = <0x8000000 0x2000000>; reg-names = "mem"; }; plic: interrupt-controller@c000000 { #interrupt-cells = <2>; compatible = "sifive,plic-1.0.0"; interrupt-controller; interrupts-extended = <&hlic 11>; reg = <0x0c000000 0x00002000 0x0c002000 0x001fe000 0x0c200000 0x03e00000>; reg-names = "prio", "irq_en", "reg"; riscv,max-priority = <7>; riscv,ndev = <52>; }; uart0: serial@10010000 { compatible = "sifive,uart0"; interrupt-parent = <&plic>; interrupts = <4 1>; reg = <0x10010000 0x1000>; reg-names = "control"; label = "uart_0"; status = "disabled"; }; uart1: serial@10011000 { compatible = "sifive,uart0"; interrupt-parent = <&plic>; interrupts = <5 1>; reg = <0x10011000 0x1000>; reg-names = "control"; label = "uart_1"; status = "disabled"; }; spi0: spi@10040000 { compatible = "sifive,spi0"; interrupt-parent = <&plic>; interrupts = <51 1>; reg = <0x10040000 0x1000 0x20000000 0x10000000>; reg-names = "control", "mem"; label = "spi_0"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@10041000 { compatible = "sifive,spi0"; interrupt-parent = <&plic>; interrupts = <52 1>; reg = <0x10041000 0x1000>; reg-names = "control"; label = "spi_1"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; spi2: spi@10050000 { compatible = "sifive,spi0"; interrupt-parent = <&plic>; interrupts = <6 1>; reg = <0x10050000 0x1000>; reg-names = "control"; label = "spi_2"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; gpio0: gpio@10060000 { compatible = "sifive,gpio0"; gpio-controller; interrupt-parent = <&plic>; interrupts = <7 1>, <8 1>, <9 1>, <10 1>, <11 1>, <12 1>, <13 1>, <14 1>, <15 1>, <16 1>, <17 1>, <18 1>, <19 1>, <20 1>, <21 1>, <22 1>; reg = <0x10060000 0x1000>; reg-names = "control"; label = "gpio_0"; status = "disabled"; #gpio-cells = <2>; #address-cells = <1>; #size-cells = <1>; ranges; }; }; }; |