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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 | /* * Copyright (c) 2018, Synopsys, Inc. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 */ #include "skeleton.dtsi" #include <zephyr/dt-bindings/i2c/i2c.h> #include <zephyr/dt-bindings/gpio/gpio.h> #define DT_APB_CLK_HZ 50000000 / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "snps,arcem"; reg = <0>; }; intc: arcv2-intc { compatible = "snps,arcv2-intc"; interrupt-controller; #interrupt-cells = <2>; }; }; sysclk: system-clock { compatible = "fixed-clock"; clock-frequency = <DT_APB_CLK_HZ>; #clock-cells = <0>; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; ddr0: memory@10000000 { device_type = "memory"; reg = <0x10000000 0x8000000>; }; i2c0: i2c@f0004000 { compatible = "snps,designware-i2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0xf0004000 0x1000>; label = "I2C_0"; interrupt-parent = <&intc>; }; i2c1: i2c@f0005000 { compatible = "snps,designware-i2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0xf0005000 0x1000>; label = "I2C_1"; interrupt-parent = <&intc>; }; uart0: uart@f0008000 { compatible = "ns16550"; clock-frequency = <DT_APB_CLK_HZ>; reg = <0xf0008000 0x1000>; label = "UART_0"; interrupt-parent = <&intc>; }; uart1: uart@f0009000 { compatible = "ns16550"; clock-frequency = <DT_APB_CLK_HZ>; reg = <0xf0009000 0x1000>; label = "UART_1"; interrupt-parent = <&intc>; }; uart2: uart@f000a000 { compatible = "ns16550"; clock-frequency = <DT_APB_CLK_HZ>; reg = <0xf000a000 0x1000>; label = "UART_2"; interrupt-parent = <&intc>; }; gpio0: gpio@f0002000 { compatible = "snps,designware-gpio"; reg = <0xf0002000 0xc>; ngpios = <32>; label = "GPIO_0"; interrupt-parent = <&intc>; gpio-controller; #gpio-cells = <2>; }; gpio1: gpio@f000200c { compatible = "snps,designware-gpio"; reg = <0xf000200c 0xc>; ngpios = <9>; label = "GPIO_1"; interrupt-parent = <&intc>; gpio-controller; #gpio-cells = <2>; }; gpio2: gpio@f0002018 { compatible = "snps,designware-gpio"; reg = <0xF0002018 0xc>; ngpios = <32>; label = "GPIO_2"; interrupt-parent = <&intc>; gpio-controller; #gpio-cells = <2>; }; gpio3: gpio@f0002024 { compatible = "snps,designware-gpio"; reg = <0xF0002024 0xc>; ngpios = <12>; label = "GPIO_3"; interrupt-parent = <&intc>; gpio-controller; #gpio-cells = <2>; }; spi0: spi@f0006000 { compatible = "snps,designware-spi"; reg = <0xf0006000 0x1000>; label = "SPI_0"; clocks = <&sysclk>; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <0>; }; spi1: spi@f0007000 { compatible = "snps,designware-spi"; reg = <0xf0007000 0x1000>; label = "SPI_1"; clocks = <&sysclk>; interrupt-parent = <&intc>; #address-cells = <1>; #size-cells = <0>; }; }; }; |