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# Copyright (c) 2017-2021, NXP
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_IMX_RT
config SOC_SERIES
default "rt"
config ROM_START_OFFSET
default 0x400 if BOOTLOADER_MCUBOOT
default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
config CAN_MCUX_FLEXCAN
default y if HAS_MCUX_FLEXCAN
depends on CAN
config CLOCK_CONTROL_MCUX_CCM
default y if HAS_MCUX_CCM
depends on CLOCK_CONTROL
config CLOCK_CONTROL_MCUX_CCM_REV2
default y if HAS_MCUX_CCM_REV2
depends on CLOCK_CONTROL
config DISPLAY_MCUX_ELCDIF
default y if HAS_MCUX_ELCDIF
depends on DISPLAY
config GPIO_MCUX_IGPIO
default y if HAS_MCUX_IGPIO
depends on GPIO
config ENTROPY_MCUX_TRNG
default y if HAS_MCUX_TRNG
depends on ENTROPY_GENERATOR
config I2C_MCUX_LPI2C
default y if HAS_MCUX_LPI2C
depends on I2C
config PWM_MCUX
default y if HAS_MCUX_PWM
depends on PWM
config ADC_MCUX_12B1MSPS_SAR
default y if HAS_MCUX_12B1MSPS_SAR
depends on ADC
config ETH_MCUX
default y if HAS_MCUX_ENET
depends on NET_L2_ETHERNET
config UART_MCUX_LPUART
default y if HAS_MCUX_LPUART
depends on SERIAL
if FLASH_MCUX_FLEXSPI_XIP
# Avoid RWW hazards by defaulting logging to disabled
choice FLASH_LOG_LEVEL_CHOICE
default FLASH_LOG_LEVEL_OFF
endchoice
choice MEMC_LOG_LEVEL_CHOICE
default MEMC_LOG_LEVEL_OFF
endchoice
endif
# set the tick per sec as a divider of the GPT clock source
config SYS_CLOCK_TICKS_PER_SEC
default 4096 if MCUX_GPT_TIMER
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if MCUX_GPT_TIMER
if COUNTER
config COUNTER_MCUX_GPT
default y if HAS_MCUX_GPT
endif # COUNTER
config SPI_MCUX_LPSPI
default y if HAS_MCUX_LPSPI
depends on SPI
config ADC_MCUX_LPADC
default y if HAS_MCUX_LPADC
depends on ADC
config WDT_MCUX_IMX_WDOG
default y
depends on WATCHDOG
config PM_MCUX_GPC
default y if HAS_MCUX_GPC
depends on SOC_SERIES_IMX_RT11XX && PM
if CODE_SEMC
config FLASH_SIZE
default $(dt_node_reg_size_int,/memory@80000000,0,K)
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/memory@80000000)
endif # CODE_SEMC
if CODE_ITCM
config FLASH_SIZE
default $(dt_node_reg_size_int,/soc/flexram@40028000/itcm@0,0,K) if SOC_SERIES_IMX_RT11XX
default $(dt_node_reg_size_int,/soc/flexram@400b0000/itcm@0,0,K) if SOC_SERIES_IMX_RT10XX
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/flexram@40028000/itcm@0) if SOC_SERIES_IMX_RT11XX
default $(dt_node_reg_addr_hex,/soc/flexram@400b0000/itcm@0) if SOC_SERIES_IMX_RT10XX
endif # CODE_ITCM
if CODE_SRAM0
config FLASH_SIZE
default $(dt_node_reg_size_int,/soc/memory@1ffe0000,0,K)
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/memory@1ffe0000)
endif # CODE_SRAM0
if CODE_FLEXSPI
config FLASH_SIZE
default $(dt_node_reg_size_int,/soc/spi@400cc000,1,K) if SOC_SERIES_IMX_RT11XX
default $(dt_node_reg_size_int,/soc/spi@402a8000,1,K) if SOC_SERIES_IMX_RT10XX
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/spi@400cc000,1) if SOC_SERIES_IMX_RT11XX
default $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) if SOC_SERIES_IMX_RT10XX
endif # CODE_FLEXSPI
if CODE_FLEXSPI2
config FLASH_SIZE
default $(dt_node_reg_size_int,/soc/spi@4000d000,1,K) if SOC_SERIES_IMX_RT11XX
default $(dt_node_reg_size_int,/soc/spi@402a4000,1,K) if SOC_SERIES_IMX_RT10XX
config FLASH_BASE_ADDRESS
default $(dt_node_reg_addr_hex,/soc/spi@4000d000,1) if SOC_SERIES_IMX_RT11XX
default $(dt_node_reg_addr_hex,/soc/spi@402a4000,1) if SOC_SERIES_IMX_RT10XX
endif # CODE_FLEXSPI2
config USB_MCUX
default y
depends on USB_DEVICE_DRIVER
choice USB_MCUX_CONTROLLER_TYPE
default USB_DC_NXP_EHCI
endchoice
config VIDEO_MCUX_CSI
default y if HAS_MCUX_CSI
depends on VIDEO
config DMA_MCUX_EDMA
default y if HAS_MCUX_EDMA
depends on DMA
DT_CHOSEN_Z_DTCM := zephyr,dtcm
choice SEGGER_RTT_SECTION
default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
depends on USE_SEGGER_RTT
endchoice
choice SEGGER_SYSVIEW_SECTION
default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM))
depends on SEGGER_SYSTEMVIEW
endchoice
#
# MBEDTLS is larger but much faster than TinyCrypt so choose wisely
#
config MBEDTLS
#config TINYCRYPT
default y if CSPRING_ENABLED
depends on ENTROPY_GENERATOR
if MBEDTLS
#
# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than
# what the ztest_thread_stack defaults to.
#
config TEST_EXTRA_STACKSIZE
int
default 1024
endif # MBEDTLS
source "soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*"
endif # SOC_SERIES_IMX_RT
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