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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 | /* * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ #include <mem.h> #include <xtensa/xtensa.dtsi> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/i2c/i2c.h> #include <dt-bindings/clock/esp32s2_clock.h> #include <dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h> / { #address-cells = <1>; #size-cells = <1>; chosen { zephyr,entropy = &trng0; zephyr,flash-controller = &flash; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "cdns,tensilica-xtensa-lx7"; reg = <0>; }; }; wifi: wifi { compatible = "espressif,esp32-wifi"; status = "disabled"; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; sram0: memory@3ffb0000 { compatible = "mmio-sram"; reg = <0x3ffb0000 0x50000>; }; intc: interrupt-controller@3f4c2000 { #interrupt-cells = <1>; compatible = "espressif,esp32-intc"; interrupt-controller; reg = <0x3f4c2000 0x114>; label = "INTC_0"; status = "okay"; }; rtc: rtc@3f408000 { compatible = "espressif,esp32-rtc"; reg = <0x3f408000 0x0D8>; label = "RTC"; xtal-freq = <ESP32_CLK_XTAL_40M>; #clock-cells = <1>; status = "ok"; }; flash: flash-controller@3f402000 { compatible = "espressif,esp32-flash-controller"; label = "FLASH_CTRL"; reg = <0x3f402000 0x1000>; #address-cells = <1>; #size-cells = <1>; flash0: flash@0 { compatible = "soc-nv-flash"; label = "FLASH_ESP32S2"; reg = <0 0x400000>; erase-block-size = <4096>; write-block-size = <4>; }; }; uart0: uart@3f400000 { compatible = "espressif,esp32-uart"; reg = <0x3f400000 0x400>; label = "UART_0"; status = "disabled"; interrupts = <UART0_INTR_SOURCE>; interrupt-parent = <&intc>; clocks = <&rtc ESP32_UART0_MODULE>; peripheral = <0>; }; uart1: uart@3f410000 { compatible = "espressif,esp32-uart"; reg = <0x3f410000 0x400>; label = "UART_1"; status = "disabled"; interrupts = <UART1_INTR_SOURCE>; interrupt-parent = <&intc>; clocks = <&rtc ESP32_UART1_MODULE>; current-speed = <115200>; peripheral = <1>; }; pinmux: pinmux@3f409000 { compatible = "espressif,esp32-pinmux"; reg = <0x3f409000 0x94>; }; gpio0: gpio@3f404000 { compatible = "espressif,esp32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x3f404000 0x800>; interrupts = <GPIO_INTR_SOURCE>; interrupt-parent = <&intc>; label = "GPIO_0"; ngpios = <32>; /* 0..31 */ }; gpio1: gpio@3f404800 { compatible = "espressif,esp32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x3f404800 0x800>; interrupts = <GPIO_INTR_SOURCE>; interrupt-parent = <&intc>; label = "GPIO_1"; ngpios = <22>; /* 32..53 */ }; i2c0: i2c@3f413000 { compatible = "espressif,esp32-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x3f413000 0x1000>; interrupts = <I2C_EXT0_INTR_SOURCE>; interrupt-parent = <&intc>; label = "I2C_0"; clocks = <&rtc ESP32_I2C0_MODULE>; status = "disabled"; }; i2c1: i2c@3f427000 { compatible = "espressif,esp32-i2c"; #address-cells = <1>; #size-cells = <0>; reg = <0x3f427000 0x1000>; interrupts = <I2C_EXT1_INTR_SOURCE>; interrupt-parent = <&intc>; label = "I2C_1"; clocks = <&rtc ESP32_I2C1_MODULE>; status = "disabled"; }; timer0: counter@3f41f000 { compatible = "espressif,esp32-timer"; reg = <0x3f41f000 DT_SIZE_K(4)>; interrupts = <TG0_T0_LEVEL_INTR_SOURCE>; interrupt-parent = <&intc>; label = "TIMG0_T0"; status = "disabled"; }; timer1: counter@3f41f024 { compatible = "espressif,esp32-timer"; reg = <0x3f41f024 DT_SIZE_K(4)>; interrupts = <TG0_T1_LEVEL_INTR_SOURCE>; interrupt-parent = <&intc>; label = "TIMG0_T1"; status = "disabled"; }; timer2: counter@3f420000 { compatible = "espressif,esp32-timer"; reg = <0x3f420000 DT_SIZE_K(4)>; interrupts = <TG1_T0_LEVEL_INTR_SOURCE>; interrupt-parent = <&intc>; label = "TIMG1_T0"; status = "disabled"; }; timer3: counter@3f420024 { compatible = "espressif,esp32-timer"; reg = <0x3f420024 DT_SIZE_K(4)>; interrupts = <TG1_T1_LEVEL_INTR_SOURCE>; interrupt-parent = <&intc>; label = "TIMG1_T1"; }; trng0: trng@3f435110 { compatible = "espressif,esp32-trng"; reg = <0x3f435110 0x4>; label = "TRNG_0"; status = "disabled"; }; spi2: spi@3f424000 { compatible = "espressif,esp32-spi"; reg = <0x3f424000 DT_SIZE_K(4)>; interrupts = <SPI2_INTR_SOURCE>; interrupt-parent = <&intc>; label = "SPI_2"; clocks = <&rtc ESP32_FSPI_MODULE>; status = "disabled"; use-iomux; }; spi3: spi@3f425000 { compatible = "espressif,esp32-spi"; reg = <0x3f425000 DT_SIZE_K(4)>; interrupts = <SPI3_INTR_SOURCE>; interrupt-parent = <&intc>; label = "SPI_3"; clocks = <&rtc ESP32_HSPI_MODULE>; status = "disabled"; }; wdt0: watchdog@3f41f048 { compatible = "espressif,esp32-watchdog"; reg = <0x3f41f048 0x20>; interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>; interrupt-parent = <&intc>; label = "WDT_0"; status = "disabled"; }; wdt1: watchdog@3f42f048 { compatible = "espressif,esp32-watchdog"; reg = <0x3f42f048 0x20>; interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>; interrupt-parent = <&intc>; label = "WDT_1"; status = "disabled"; }; }; }; |