# MIMXRT1160-EVK board

# Copyright (c) 2021, NXP
# SPDX-License-Identifier: Apache-2.0

if BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4

config BOARD
	default "mimxrt1160_evk_cm7" if BOARD_MIMXRT1160_EVK_CM7
	default "mimxrt1160_evk_cm4" if BOARD_MIMXRT1160_EVK_CM4

choice CODE_LOCATION
	default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7
	default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4
endchoice

config SYS_CLOCK_HW_CYCLES_PER_SEC
	default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK
	default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK

if FLASH

config FLASH_MCUX_FLEXSPI_NOR
	default y

# XIP will not be enabled if CPU is cortex m4, since code is flashed to SRAM
config FLASH_MCUX_FLEXSPI_XIP
	default y if CPU_CORTEX_M7

choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
	default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7
	default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4
endchoice

endif #FLASH

if NETWORKING

config NET_L2_ETHERNET
	default y if CPU_CORTEX_M7 # No cache memory support is required for driver

endif # NETWORKING

endif # BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4