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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 | /* * Copyright (c) 2019 Intel Corporation. * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; #include <espressif/esp32.dtsi> / { model = "esp32"; compatible = "espressif,esp32"; aliases { uart-0 = &uart0; i2c-0 = &i2c0; }; chosen { zephyr,sram = &sram0; zephyr,console = &uart0; zephyr,shell-uart = &uart0; zephyr,flash = &flash0; }; }; &cpu0 { clock-frequency = <ESP32_CLK_CPU_240M>; }; &cpu1 { clock-frequency = <ESP32_CLK_CPU_240M>; }; &uart0 { status = "okay"; current-speed = <115200>; tx-pin = <1>; rx-pin = <3>; rts-pin = <22>; cts-pin = <19>; }; &uart1 { current-speed = <115200>; tx-pin = <10>; rx-pin = <9>; rts-pin = <11>; cts-pin = <6>; hw-flow-control; }; &uart2 { current-speed = <115200>; tx-pin = <17>; rx-pin = <16>; rts-pin = <7>; cts-pin = <8>; hw-flow-control; }; &i2c0 { status = "okay"; clock-frequency = <I2C_BITRATE_FAST>; sda-pin = <21>; scl-pin = <22>; }; &i2c1 { clock-frequency = <I2C_BITRATE_FAST>; sda-pin = <18>; scl-pin = <5>; }; &spi2 { #address-cells = <1>; #size-cells = <0>; status = "okay"; miso-pin = <12>; mosi-pin = <13>; sclk-pin = <14>; csel-pin = <15>; }; &spi3 { #address-cells = <1>; #size-cells = <0>; status = "okay"; miso-pin = <19>; mosi-pin = <23>; sclk-pin = <18>; csel-pin = <5>; }; &timer0 { status = "okay"; }; &timer1 { status = "okay"; }; &timer2 { status = "okay"; }; &timer3 { status = "okay"; }; &trng0 { status = "okay"; }; &flash0 { status = "okay"; partitions { compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; storage_partition: partition@9000 { label = "storage"; reg = <0x00009000 0x00006000>; }; }; }; |