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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 | /* * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 */ #define DT_DRV_COMPAT espressif_esp32_timer /* Include esp-idf headers first to avoid redefining BIT() macro */ #include <soc/rtc_cntl_reg.h> #include <soc/timer_group_reg.h> #include <driver/periph_ctrl.h> #include <soc/periph_defs.h> #include <hal/timer_types.h> #include <hal/timer_hal.h> #include <string.h> #include <drivers/counter.h> #include <drivers/interrupt_controller/intc_esp32.h> #include <device.h> #include <logging/log.h> LOG_MODULE_REGISTER(esp32_counter, CONFIG_COUNTER_LOG_LEVEL); #define INITIAL_COUNT (0x00000000ULL) #define INST_0_INDEX TIMER_0 #define INST_1_INDEX TIMER_1 #define INST_2_INDEX TIMER_0 #define INST_3_INDEX TIMER_1 #define INST_0_GROUP TIMER_GROUP_0 #define INST_1_GROUP TIMER_GROUP_0 #define INST_2_GROUP TIMER_GROUP_1 #define INST_3_GROUP TIMER_GROUP_1 #define TIMX p_timer_obj[TIMG(dev)][TIDX(dev)] #define DEV_CFG(dev) ((const struct counter_esp32_config *const)(dev)->config) #define DEV_DATA(dev) ((struct counter_esp32_data *)(dev)->data) #define TIMG(dev) (DEV_CFG(dev)->group) #define TIDX(dev) (DEV_CFG(dev)->idx) static void counter_esp32_isr(void *arg); typedef bool (*timer_isr_t)(void *); struct timer_isr_func_t { timer_isr_t fn; void *args; struct intr_handle_data_t *timer_isr_handle; timer_group_t isr_timer_group; }; struct counter_obj_t { timer_hal_context_t hal; struct timer_isr_func_t timer_isr_fun; }; struct counter_esp32_config { struct counter_config_info counter_info; timer_config_t config; timer_group_t group; timer_idx_t idx; int irq_source; }; struct counter_esp32_data { struct counter_alarm_cfg alarm_cfg; uint32_t ticks; }; static struct counter_obj_t *p_timer_obj[TIMER_GROUP_MAX][TIMER_MAX] = { 0 }; static struct k_spinlock lock; static int counter_esp32_init(const struct device *dev) { const struct counter_esp32_config *cfg = DEV_CFG(dev); if (TIMG(dev) == TIMER_GROUP_0) { periph_module_enable(PERIPH_TIMG0_MODULE); } else if (TIMG(dev) == TIMER_GROUP_1) { periph_module_enable(PERIPH_TIMG1_MODULE); } else { return -ENOTSUP; } if (TIMX == NULL) { TIMX = (struct counter_obj_t *)k_calloc(1, sizeof(struct counter_obj_t)); if (TIMX == NULL) { LOG_ERR("TIMER driver malloc error"); return -ENOMEM; } } k_spinlock_key_t key = k_spin_lock(&lock); timer_hal_init(&TIMX->hal, TIMG(dev), TIDX(dev)); DEV_DATA(dev)->alarm_cfg.callback = NULL; timer_hal_intr_disable(&TIMX->hal); timer_hal_clear_intr_status(&TIMX->hal); timer_hal_set_auto_reload(&TIMX->hal, cfg->config.auto_reload); timer_hal_set_divider(&TIMX->hal, cfg->config.divider); timer_hal_set_counter_increase(&TIMX->hal, cfg->config.counter_dir); timer_hal_set_alarm_enable(&TIMX->hal, cfg->config.alarm_en); if (cfg->config.intr_type == TIMER_INTR_LEVEL) { timer_hal_set_level_int_enable(&TIMX->hal, true); } timer_hal_set_counter_value(&TIMX->hal, INITIAL_COUNT); timer_hal_set_counter_enable(&TIMX->hal, cfg->config.counter_en); esp_intr_alloc(DEV_CFG(dev)->irq_source, 0, counter_esp32_isr, (void *)dev, NULL); k_spin_unlock(&lock, key); return 0; } static int counter_esp32_start(const struct device *dev) { k_spinlock_key_t key = k_spin_lock(&lock); timer_hal_set_counter_enable(&TIMX->hal, TIMER_START); k_spin_unlock(&lock, key); return 0; } static int counter_esp32_stop(const struct device *dev) { k_spinlock_key_t key = k_spin_lock(&lock); timer_hal_set_counter_enable(&TIMX->hal, TIMER_PAUSE); k_spin_unlock(&lock, key); return 0; } static int counter_esp32_get_value(const struct device *dev, uint32_t *ticks) { k_spinlock_key_t key = k_spin_lock(&lock); timer_hal_get_counter_value(&TIMX->hal, (uint64_t *)ticks); k_spin_unlock(&lock, key); return 0; } static int counter_esp32_set_alarm(const struct device *dev, uint8_t chan_id, const struct counter_alarm_cfg *alarm_cfg) { ARG_UNUSED(chan_id); uint32_t now; counter_esp32_get_value(dev, &now); k_spinlock_key_t key = k_spin_lock(&lock); timer_hal_set_alarm_value(&TIMX->hal, (now + alarm_cfg->ticks)); timer_hal_intr_enable(&TIMX->hal); timer_hal_set_alarm_enable(&TIMX->hal, TIMER_ALARM_EN); DEV_DATA(dev)->alarm_cfg.callback = alarm_cfg->callback; DEV_DATA(dev)->alarm_cfg.user_data = alarm_cfg->user_data; k_spin_unlock(&lock, key); return 0; } static int counter_esp32_cancel_alarm(const struct device *dev, uint8_t chan_id) { ARG_UNUSED(chan_id); k_spinlock_key_t key = k_spin_lock(&lock); timer_hal_intr_disable(&TIMX->hal); timer_hal_set_alarm_enable(&TIMX->hal, TIMER_ALARM_DIS); k_spin_unlock(&lock, key); return 0; } static int counter_esp32_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg) { if (cfg->ticks != (DEV_CFG(dev))->counter_info.max_top_value) { return -ENOTSUP; } else { return 0; } } static uint32_t counter_esp32_get_pending_int(const struct device *dev) { timer_hal_get_intr_status_reg(&TIMX->hal); return 0; } static uint32_t counter_esp32_get_top_value(const struct device *dev) { return DEV_CFG(dev)->counter_info.max_top_value; } static const struct counter_driver_api counter_api = { .start = counter_esp32_start, .stop = counter_esp32_stop, .get_value = counter_esp32_get_value, .set_alarm = counter_esp32_set_alarm, .cancel_alarm = counter_esp32_cancel_alarm, .set_top_value = counter_esp32_set_top_value, .get_pending_int = counter_esp32_get_pending_int, .get_top_value = counter_esp32_get_top_value, }; static void counter_esp32_isr(void *arg) { struct device *dev = (struct device *)arg; counter_esp32_cancel_alarm(dev, 0); uint32_t now; counter_esp32_get_value(dev, &now); struct counter_alarm_cfg *alarm_cfg = &DEV_DATA(dev)->alarm_cfg; if (alarm_cfg->callback) { alarm_cfg->callback(dev, 0, now, alarm_cfg->user_data); } timer_hal_clear_intr_status(&TIMX->hal); } #define ESP32_COUNTER_INIT(n) \ \ static struct counter_esp32_data counter_data_##n; \ \ static const struct counter_esp32_config counter_config_##n = { \ .counter_info = { \ .max_top_value = UINT32_MAX, \ .freq = (APB_CLK_FREQ / CONFIG_COUNTER_ESP32_PRESCALER), \ .flags = COUNTER_CONFIG_INFO_COUNT_UP, \ .channels = 1 \ }, \ .config = { \ .alarm_en = TIMER_ALARM_DIS, \ .counter_en = TIMER_START, \ .intr_type = TIMER_INTR_LEVEL, \ .counter_dir = TIMER_COUNT_UP, \ .auto_reload = TIMER_AUTORELOAD_DIS, \ .divider = CONFIG_COUNTER_ESP32_PRESCALER, \ }, \ .group = INST_##n##_GROUP, \ .idx = INST_##n##_INDEX, \ .irq_source = DT_IRQN(DT_NODELABEL(timer##n)) \ }; \ \ \ DEVICE_DT_INST_DEFINE(n, \ counter_esp32_init, \ NULL, &counter_data_##n, \ &counter_config_##n, PRE_KERNEL_1, \ CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &counter_api); #ifdef CONFIG_COUNTER_ESP32_TG0_T0 ESP32_COUNTER_INIT(0); #endif #ifdef CONFIG_COUNTER_ESP32_TG0_T1 ESP32_COUNTER_INIT(1); #endif #ifdef CONFIG_COUNTER_ESP32_TG1_T0 ESP32_COUNTER_INIT(2); #endif #ifdef CONFIG_COUNTER_ESP32_TG1_T1 ESP32_COUNTER_INIT(3); #endif |