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# STM32L4, STM32L5, STM32WB and STM32WL PLL configuration options

# Copyright (c) 2019 Linaro
# SPDX-License-Identifier: Apache-2.0

if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX

config CLOCK_STM32_PLL_M_DIVISOR
	int "PLL divisor"
	depends on CLOCK_STM32_SYSCLK_SRC_PLL
	default 1
	range 1 8 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
	range 1 16 if SOC_SERIES_STM32L5X
	help
	  PLL divisor,
	  L4: allowed values: 1-8. PLL VCO input ranges from 4 to 16MHz
	  L5: allowed values: 1-16. PLL VCO input ranges from 4 to 16MHz
	  WB: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz
	  WL: allowed values: 1-8. PLL VCO input ranges from 2.66 to 16MHz

config CLOCK_STM32_PLL_N_MULTIPLIER
	int "PLL multiplier"
	depends on CLOCK_STM32_SYSCLK_SRC_PLL
	default 20
	range 8 86 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X
	range 6 127 if SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
	help
	  PLL multiplier,
	  L4: allowed values: 8-86. PLL VCO output ranges from 64 to 334MHz
	  L5: allowed values: 8-86. PLL VCO output ranges from 64 to 334MHz
	  WB: allowed values: 6-127. PLL VCO output ranges from 96 to 334MHz
	  WL: allowed values: 6-127. PLL VCO output ranges from 96 to 334MHz

config CLOCK_STM32_PLL_P_DIVISOR
	int "PLL P Divisor"
	depends on CLOCK_STM32_SYSCLK_SRC_PLL
	default 7
	range 0 17 if SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X
	range 0 32 if SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX
	help
	  PLL P Output divisor
	  L4: allowed values: 0, 7, 17. PLLP do not exceed 80MHz
	  L5: allowed values: 0, 7, 17. PLLP do not exceed 80MHz
	  WB: allowed values: 0, 2-32. PLLP do not exceed 64MHz
	  WL: allowed values: 0, 2-32. PLLP do not exceed 48MHz

config CLOCK_STM32_PLL_Q_DIVISOR
	int "PLL Q Divisor"
	depends on CLOCK_STM32_SYSCLK_SRC_PLL
	default 2
	range 0 8
	help
	  PLL Q Output divisor
	  L4: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz
	  L5: allowed values: 0, 2, 4, 6, 8. PLLQ do not exceed 80MHz
	  WB: allowed values: 0, 2-8. PLLQ do not exceed 64MHz
	  WL: allowed values: 0, 2-8. PLLQ do not exceed 48MHz

config CLOCK_STM32_PLL_R_DIVISOR
	int "PLL R Divisor"
	depends on CLOCK_STM32_SYSCLK_SRC_PLL
	default 4
	range 0 8
	help
	  PLL R Output divisor
	  L4: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 80MHz
	  L5: allowed values: 0, 2, 4, 6, 8. PLLR do not exceed 110MHz
	  WB: allowed values: 0, 2-8. PLLR do not exceed 64MHz
	  WL: allowed values: 0, 2-8. PLLR do not exceed 48MHz

config CLOCK_STM32_LSE
	bool "Low-speed external clock"
	help
	  Enable the low-speed external (LSE) clock supplied with a 32.768 kHz
	  crystal resonator oscillator.

config CLOCK_STM32_MSI_PLL_MODE
	bool "MSI PLL MODE"
	depends on CLOCK_STM32_LSE
	help
	  Enable hardware auto-calibration with LSE.

endif # SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX