Linux debugging

Check our new training course

Linux debugging, tracing, profiling & perf. analysis

Check our new training course
with Creative Commons CC-BY-SA
lecture and lab materials

Bootlin logo

Elixir Cross Referencer

Open Menu /boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts 
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
/*
 * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <mem.h>
#include <arm64/armv8-r.dtsi>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "FVP BaseR AEMv8R";

	chosen {
		/*
		 * The SRAM node is actually located in the
		 * DRAM region of the FVP BaseR AEMv8R.
		 */
		zephyr,sram = &dram0;
		zephyr,flash = &flash0;
		zephyr,console = &uart0;
		zephyr,shell-uart = &uart0;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "hvc";
		label = "PSCI";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-r82";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-r82";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-r82";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-r82";
			reg = <3>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>;
		label = "arch_timer";
	};

	uartclk: apb-pclk {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		#clock-cells = <0>;
	};

	soc {
		interrupt-parent = <&gic>;

		gic: interrupt-controller@af000000 {
			compatible = "arm,gic";
			reg = <0xaf000000 0x1000>,
			      <0xaf100000 0x100>;
			interrupt-controller;
			#interrupt-cells = <4>;
			label = "GIC";
			status = "okay";
		};

		uart0: uart@9c090000 {
			compatible = "arm,pl011";
			reg = <0x9c090000 0x1000>;
			status = "disabled";
			interrupts = <GIC_SPI 1 0 IRQ_TYPE_LEVEL>;
			interrupt-names = "irq_0";
			label = "UART_0";
			clocks = <&uartclk>;
		};

		flash0: flash@0 {
			compatible = "soc-nv-flash";
			reg = <0x0 DT_SIZE_K(64)>;
		};

		dram0: memory@10000000 {
			compatible = "mmio-dram";
			reg = <0x10000000 DT_SIZE_K(2048)>;
		};
	};
};

&uart0 {
	status = "okay";
	current-speed = <115200>;
};