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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 | # Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com> # SPDX-License-Identifier: Apache-2.0 menu "RISCV Options" depends on RISCV config ARCH string default "riscv64" if 64BIT default "riscv32" config COMPRESSED_ISA bool default y if 64BIT config FLOAT_HARD bool "Enable hard-float calling convention" default y depends on FPU help This option enables the hard-float calling convention. config RISCV_GP bool "Enable RISC-V global pointer relative addressing" default n help Use global pointer relative addressing for small globals declared anywhere in the executable. It can benefit performance and reduce the code size. Note: To support this feature, RISC-V SoC needs to initialize global pointer at program start or earlier than any instruction using GP relative addressing. menu "RISCV Processor Options" config CORE_E31 bool "Use E31 core" select RISCV_PMP select ARCH_HAS_USERSPACE select ARCH_HAS_STACK_PROTECTION if PMP_STACK_GUARD default n help This option signifies the use of a core of the E31 family. config INCLUDE_RESET_VECTOR bool "Include Reset vector" help Include the reset vector stub, which initializes the stack and prepares for running C code. config RISCV_SOC_CONTEXT_SAVE bool "Enable SOC-based context saving in IRQ handlers" select RISCV_SOC_OFFSETS help Enable low-level SOC-specific context management, for SOCs with extra state that must be saved when entering an interrupt/exception, and restored on exit. If unsure, leave this at the default value. Enabling this option requires that the SoC provide a soc_context.h header which defines the following macros: - SOC_ESF_MEMBERS: structure component declarations to allocate space for. The last such declaration should not end in a semicolon, for portability. The generic RISC-V architecture code will allocate space for these members in a "struct soc_esf" type (typedefed to soc_esf_t), which will be available if arch.h is included. - SOC_ESF_INIT: structure contents initializer for struct soc_esf state. The last initialized member should not end in a comma. The generic architecture IRQ wrapper will also call \_\_soc_save_context and \_\_soc_restore_context routines at ISR entry and exit, respectively. These should typically be implemented in assembly. If they were C functions, they would have these signatures: ``void __soc_save_context(soc_esf_t *state);`` ``void __soc_restore_context(soc_esf_t *state);`` The calls obey standard calling conventions; i.e., the state pointer address is in a0, and ra contains the return address. config RISCV_SOC_OFFSETS bool "Enable SOC-based offsets" help Enabling this option requires that the SoC provide a soc_offsets.h header which defines the following macros: - GEN_SOC_OFFSET_SYMS(): a macro which expands to GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls to ensure offset macros for SOC_ESF_MEMBERS are defined in offsets.h. The last one should not end in a semicolon. See gen_offset.h for more details. config RISCV_SOC_INTERRUPT_INIT bool "Enable SOC-based interrupt initialization" help Enable SOC-based interrupt initialization (call soc_interrupt_init, within _IntLibInit when enabled) config RISCV_GENERIC_TOOLCHAIN bool "Compile using generic riscv32 toolchain" default y help Compile using generic riscv32 toolchain. Allow SOCs that have custom extended riscv ISA to still compile with generic riscv32 toolchain. config RISCV_HAS_CPU_IDLE bool "Does SOC has CPU IDLE instruction" help Does SOC has CPU IDLE instruction config GEN_ISR_TABLES default y config GEN_IRQ_VECTOR_TABLE default n config NUM_IRQS int menuconfig RISCV_PMP bool "RISC-V PMP Support" default n select THREAD_STACK_INFO select CPU_HAS_MPU select MPU select SRAM_REGION_PERMISSIONS select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE select PMP_POWER_OF_TWO_ALIGNMENT if USERSPACE help MCU implements Physical Memory Protection. Memory protection against read-only area writing is natively supported on real HW. if RISCV_PMP source "arch/riscv/core/pmp/Kconfig" endif #RISCV_PMP endmenu config MAIN_STACK_SIZE default 4096 if 64BIT config TEST_EXTRA_STACKSIZE default 1024 config CMSIS_THREAD_MAX_STACK_SIZE default 1024 if 64BIT config CMSIS_V2_THREAD_MAX_STACK_SIZE default 1024 if 64BIT endmenu |