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* Copyright (c) 2019 Argentum Systems Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f1/stm32f1.dtsi>
/ {
clocks {
/delete-node/ pll;
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f105-pll-clock";
status = "disabled";
};
pll2: pll2 {
#clock-cells = <0>;
compatible = "st,stm32f105-pll2-clock";
clocks = <&clk_hse>;
status = "disabled";
};
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <DT_SIZE_K(2)>;
};
};
can1: can@40006400 {
compatible = "st,stm32-can";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
bus-speed = <250000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
can2: can@40006800 {
compatible = "st,stm32-can";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40006800 0x400>;
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
status = "disabled";
label = "CAN_2";
bus-speed = <250000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
timers5: timers@40000c00 {
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
interrupts = <50 0>;
interrupt-names = "global";
status = "disabled";
label = "TIMERS_5";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
st,prescaler = <0>;
label = "PWM_5";
#pwm-cells = <3>;
};
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <54 0>;
interrupt-names = "global";
status = "disabled";
label = "TIMERS_6";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
st,prescaler = <0>;
label = "PWM_6";
#pwm-cells = <3>;
};
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
interrupts = <55 0>;
interrupt-names = "global";
status = "disabled";
label = "TIMERS_7";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
st,prescaler = <0>;
label = "PWM_7";
#pwm-cells = <3>;
};
};
usbotg_fs: usb@50000000 {
compatible = "st,stm32-otgfs";
reg = <0x50000000 0x40000>;
interrupts = <67 0>;
interrupt-names = "otgfs";
num-bidir-endpoints = <4>;
ram-size = <1280>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00001000>;
phys = <&otgfs_phy>;
status = "disabled";
label = "OTGFS";
};
};
otgfs_phy: otgfs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "OTGFS_PHY";
};
};
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