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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 | /* * Copyright (c) 2017 Linaro Limited. * * SPDX-License-Identifier: Apache-2.0 */ #include <device.h> #include <init.h> #include <kernel.h> #include <soc.h> #include "arm_core_mpu_dev.h" #include <linker/linker-defs.h> #include <kernel_arch_data.h> #define LOG_LEVEL CONFIG_MPU_LOG_LEVEL #include <logging/log.h> LOG_MODULE_DECLARE(mpu); #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) /* The order here is on purpose since ARMv8-M SoCs may define * CONFIG_ARMV6_M_ARMV8_M_BASELINE or CONFIG_ARMV7_M_ARMV8_M_MAINLINE * so we want to check for ARMv8-M first. */ #define MPU_NODEID DT_INST(0, arm_armv8m_mpu) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) #define MPU_NODEID DT_INST(0, arm_armv7m_mpu) #elif defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) #define MPU_NODEID DT_INST(0, arm_armv6m_mpu) #endif #if DT_NODE_HAS_PROP(MPU_NODEID, arm_num_mpu_regions) #define NUM_MPU_REGIONS DT_PROP(MPU_NODEID, arm_num_mpu_regions) #endif /* * Global status variable holding the number of HW MPU region indices, which * have been reserved by the MPU driver to program the static (fixed) memory * regions. */ static uint8_t static_regions_num; /* Include architecture-specific internal headers. */ #if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ defined(CONFIG_CPU_CORTEX_M3) || \ defined(CONFIG_CPU_CORTEX_M4) || \ defined(CONFIG_CPU_CORTEX_M7) || \ defined(CONFIG_CPU_CORTEX_R) #include "arm_mpu_v7_internal.h" #elif defined(CONFIG_CPU_CORTEX_M23) || \ defined(CONFIG_CPU_CORTEX_M33) || \ defined(CONFIG_CPU_CORTEX_M55) #include "arm_mpu_v8_internal.h" #else #error "Unsupported ARM CPU" #endif static int region_allocate_and_init(const uint8_t index, const struct arm_mpu_region *region_conf) { /* Attempt to allocate new region index. */ if (index > (get_num_regions() - 1U)) { /* No available MPU region index. */ LOG_ERR("Failed to allocate new MPU region %u\n", index); return -EINVAL; } LOG_DBG("Program MPU region at index 0x%x", index); /* Program region */ region_init(index, region_conf); return index; } /* This internal function programs an MPU region * of a given configuration at a given MPU index. */ static int mpu_configure_region(const uint8_t index, const struct z_arm_mpu_partition *new_region) { struct arm_mpu_region region_conf; LOG_DBG("Configure MPU region at index 0x%x", index); /* Populate internal ARM MPU region configuration structure. */ region_conf.base = new_region->start; #if defined(CONFIG_CPU_CORTEX_R) region_conf.size = size_to_mpu_rasr_size(new_region->size); #endif get_region_attr_from_mpu_partition_info(®ion_conf.attr, &new_region->attr, new_region->start, new_region->size); /* Allocate and program region */ return region_allocate_and_init(index, (const struct arm_mpu_region *)®ion_conf); } #if !defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) || \ !defined(CONFIG_MPU_GAP_FILLING) /* This internal function programs a set of given MPU regions * over a background memory area, optionally performing a * sanity check of the memory regions to be programmed. */ static int mpu_configure_regions(const struct z_arm_mpu_partition regions[], uint8_t regions_num, uint8_t start_reg_index, bool do_sanity_check) { int i; int reg_index = start_reg_index; for (i = 0; i < regions_num; i++) { if (regions[i].size == 0U) { continue; } /* Non-empty region. */ if (do_sanity_check && (!mpu_partition_is_valid(®ions[i]))) { LOG_ERR("Partition %u: sanity check failed.", i); return -EINVAL; } reg_index = mpu_configure_region(reg_index, ®ions[i]); if (reg_index == -EINVAL) { return reg_index; } /* Increment number of programmed MPU indices. */ reg_index++; } return reg_index; } #endif /* ARM Core MPU Driver API Implementation for ARM MPU */ #if defined(CONFIG_CPU_CORTEX_R) /** * @brief enable the MPU by setting bit in SCTRL register */ void arm_core_mpu_enable(void) { uint32_t val; __asm__ volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) ::); val |= SCTRL_MPU_ENABLE; /* Make sure that all the registers are set before proceeding */ __asm__ volatile ("dsb"); __asm__ volatile ("mcr p15, 0, %0, c1, c0, 0" :: "r" (val) :); __asm__ volatile ("isb"); } /** * @brief disable the MPU by clearing bit in SCTRL register */ void arm_core_mpu_disable(void) { uint32_t val; __asm__ volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val) ::); val &= ~SCTRL_MPU_ENABLE; /* Force any outstanding transfers to complete before disabling MPU */ __asm__ volatile ("dsb"); __asm__ volatile ("mcr p15, 0, %0, c1, c0, 0" :: "r" (val) :); __asm__ volatile ("isb"); } #else /** * @brief enable the MPU */ void arm_core_mpu_enable(void) { /* Enable MPU and use the default memory map as a * background region for privileged software access. */ MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_PRIVDEFENA_Msk; /* Make sure that all the registers are set before proceeding */ __DSB(); __ISB(); } /** * @brief disable the MPU */ void arm_core_mpu_disable(void) { /* Force any outstanding transfers to complete before disabling MPU */ __DMB(); /* Disable MPU */ MPU->CTRL = 0; } #endif #if defined(CONFIG_USERSPACE) /** * @brief update configuration of an active memory partition */ void arm_core_mpu_mem_partition_config_update( struct z_arm_mpu_partition *partition, k_mem_partition_attr_t *new_attr) { /* Find the partition. ASSERT if not found. */ uint8_t i; uint8_t reg_index = get_num_regions(); for (i = get_dyn_region_min_index(); i < get_num_regions(); i++) { if (!is_enabled_region(i)) { continue; } uint32_t base = mpu_region_get_base(i); if (base != partition->start) { continue; } uint32_t size = mpu_region_get_size(i); if (size != partition->size) { continue; } /* Region found */ reg_index = i; break; } __ASSERT(reg_index != get_num_regions(), "Memory domain partition %p size %zu not found\n", (void *)partition->start, partition->size); /* Modify the permissions */ partition->attr = *new_attr; mpu_configure_region(reg_index, partition); } /** * @brief get the maximum number of available (free) MPU region indices * for configuring dynamic MPU partitions */ int arm_core_mpu_get_max_available_dyn_regions(void) { return get_num_regions() - static_regions_num; } /** * @brief validate the given buffer is user accessible or not * * Presumes the background mapping is NOT user accessible. */ int arm_core_mpu_buffer_validate(void *addr, size_t size, int write) { return mpu_buffer_validate(addr, size, write); } #endif /* CONFIG_USERSPACE */ /** * @brief configure fixed (static) MPU regions. */ void arm_core_mpu_configure_static_mpu_regions(const struct z_arm_mpu_partition static_regions[], const uint8_t regions_num, const uint32_t background_area_start, const uint32_t background_area_end) { if (mpu_configure_static_mpu_regions(static_regions, regions_num, background_area_start, background_area_end) == -EINVAL) { __ASSERT(0, "Configuring %u static MPU regions failed\n", regions_num); } } #if defined(CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS) /** * @brief mark memory areas for dynamic region configuration */ void arm_core_mpu_mark_areas_for_dynamic_regions( const struct z_arm_mpu_partition dyn_region_areas[], const uint8_t dyn_region_areas_num) { if (mpu_mark_areas_for_dynamic_regions(dyn_region_areas, dyn_region_areas_num) == -EINVAL) { __ASSERT(0, "Marking %u areas for dynamic regions failed\n", dyn_region_areas_num); } } #endif /* CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS */ /** * @brief configure dynamic MPU regions. */ void arm_core_mpu_configure_dynamic_mpu_regions(const struct z_arm_mpu_partition dynamic_regions[], uint8_t regions_num) { if (mpu_configure_dynamic_mpu_regions(dynamic_regions, regions_num) == -EINVAL) { __ASSERT(0, "Configuring %u dynamic MPU regions failed\n", regions_num); } } /* ARM MPU Driver Initial Setup */ /* * @brief MPU default configuration * * This function provides the default configuration mechanism for the Memory * Protection Unit (MPU). */ int z_arm_mpu_init(void) { uint32_t r_index; if (mpu_config.num_regions > get_num_regions()) { /* Attempt to configure more MPU regions than * what is supported by hardware. As this operation * is executed during system (pre-kernel) initialization, * we want to ensure we can detect an attempt to * perform invalid configuration. */ __ASSERT(0, "Request to configure: %u regions (supported: %u)\n", mpu_config.num_regions, get_num_regions() ); return -1; } LOG_DBG("total region count: %d", get_num_regions()); arm_core_mpu_disable(); #if defined(CONFIG_NOCACHE_MEMORY) /* Clean and invalidate data cache if it is enabled and * that was not already done at boot */ #if !defined(CONFIG_INIT_ARCH_HW_AT_BOOT) if (SCB->CCR & SCB_CCR_DC_Msk) { SCB_CleanInvalidateDCache(); } #endif #endif /* CONFIG_NOCACHE_MEMORY */ /* Architecture-specific configuration */ mpu_init(); /* Program fixed regions configured at SOC definition. */ for (r_index = 0U; r_index < mpu_config.num_regions; r_index++) { region_init(r_index, &mpu_config.mpu_regions[r_index]); } /* Update the number of programmed MPU regions. */ static_regions_num = mpu_config.num_regions; arm_core_mpu_enable(); /* Program additional fixed flash region for null-pointer * dereferencing detection (debug feature) */ #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU) #if (defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)) && \ (CONFIG_FLASH_BASE_ADDRESS > CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) #pragma message "Null-Pointer exception detection cannot be configured on un-mapped flash areas" #else const struct z_arm_mpu_partition unmap_region = { .start = 0x0, .size = CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE, #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) /* Overlapping region (with any permissions) * will result in fault generation */ .attr = K_MEM_PARTITION_P_RO_U_NA, #else /* Explicit no-access policy */ .attr = K_MEM_PARTITION_P_NA_U_NA, #endif }; /* The flash region for null pointer dereferencing detection shall * comply with the regular MPU partition definition restrictions * (size and alignment). */ _ARCH_MEM_PARTITION_ALIGN_CHECK(0x0, CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE); #if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) /* ARMv8-M requires that the area: * 0x0 - CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE * is not unmapped (belongs to a valid MPU region already). */ if ((arm_cmse_mpu_region_get(0x0) == -EINVAL) || (arm_cmse_mpu_region_get( CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1) == -EINVAL)) { __ASSERT(0, "Null pointer detection page unmapped\n"); } #endif if (mpu_configure_region(static_regions_num, &unmap_region) == -EINVAL) { __ASSERT(0, "Programming null-pointer detection region failed\n"); return -EINVAL; } static_regions_num++; #endif #endif /* CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU */ /* Sanity check for number of regions in Cortex-M0+, M3, and M4. */ #if defined(CONFIG_CPU_CORTEX_M0PLUS) || \ defined(CONFIG_CPU_CORTEX_M3) || \ defined(CONFIG_CPU_CORTEX_M4) __ASSERT( (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos == 8, "Invalid number of MPU regions\n"); #elif defined(NUM_MPU_REGIONS) __ASSERT( (MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos == NUM_MPU_REGIONS, "Invalid number of MPU regions\n"); #endif /* CORTEX_M0PLUS || CPU_CORTEX_M3 || CPU_CORTEX_M4 */ return 0; } |