Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 | /*
* Copyright (c) 2017, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for nxp_lpc55s69 platform
*
* This module provides routines to initialize and support board-level
* hardware for the nxp_lpc55s69 platform.
*/
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <drivers/uart.h>
#include <linker/sections.h>
#include <arch/cpu.h>
#include <aarch32/cortex_m/exc.h>
#include <fsl_power.h>
#include <fsl_clock.h>
#include <fsl_common.h>
#include <fsl_device_registers.h>
#include <fsl_pint.h>
/**
*
* @brief Initialize the system clock
*
* @return N/A
*
*/
static ALWAYS_INLINE void clock_init(void)
{
#if defined(CONFIG_SOC_LPC55S16) || defined(CONFIG_SOC_LPC55S28) || \
defined(CONFIG_SOC_LPC55S69_CPU0)
/*!< Set up the clock sources */
/*!< Configure FRO192M */
/*!< Ensure FRO is on */
POWER_DisablePD(kPDRUNCFG_PD_FRO192M);
/*!< Set up FRO to the 12 MHz, just for sure */
CLOCK_SetupFROClocking(12000000U);
/*!< Switch to FRO 12MHz first to ensure we can change the clock */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
/* Enable FRO HF(96MHz) output */
CLOCK_SetupFROClocking(96000000U);
#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
/*!< Set FLASH wait states for core */
CLOCK_SetFLASHAccessCyclesForFreq(96000000U);
#endif
/*!< Set up dividers */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);
/*!< Set up clock selectors - Attach clocks to the peripheries */
CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
/* Enables the clock for the I/O controller.: Enable Clock. */
CLOCK_EnableClock(kCLOCK_Iocon);
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay)
/* attach 12 MHz clock to FLEXCOMM4 */
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
/* reset FLEXCOMM for I2C */
RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(hs_lspi), okay)
/* Attach 12 MHz clock to HSLSPI */
CLOCK_AttachClk(kFRO_HF_DIV_to_HSLSPI);
/* reset HSLSPI for SPI */
RESET_PeripheralReset(kHSLSPI_RST_SHIFT_RSTn);
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay)
/* Enable 1 MHz FRO clock for WWDT */
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;
#endif
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(mailbox0), nxp_lpc_mailbox, okay)
CLOCK_EnableClock(kCLOCK_Mailbox);
/* Reset the MAILBOX module */
RESET_PeripheralReset(kMAILBOX_RST_SHIFT_RSTn);
#endif
#endif /* CONFIG_SOC_LPC55S69_CPU0 */
}
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
static int nxp_lpc55xxx_init(const struct device *arg)
{
ARG_UNUSED(arg);
/* old interrupt lock level */
unsigned int oldLevel;
/* disable interrupts */
oldLevel = irq_lock();
z_arm_clear_faults();
/* Initialize FRO/system clock to 96 MHz */
clock_init();
#ifdef CONFIG_GPIO_MCUX_LPC
/* Turn on PINT device*/
PINT_Init(PINT);
#endif
/*
* install default handler that simply resets the CPU if configured in
* the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
SYS_INIT(nxp_lpc55xxx_init, PRE_KERNEL_1, 0);
#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC55S69_CPU0)
/**
*
* @brief Second Core Init
*
* This routine boots the secondary core
* @return N/A
*/
/* This function is also called at deep sleep resume. */
int _second_core_init(const struct device *arg)
{
int32_t temp;
ARG_UNUSED(arg);
/* Setup the reset handler pointer (PC) and stack pointer value.
* This is used once the second core runs its startup code.
* The second core first boots from flash (address 0x00000000)
* and then detects its identity (Core no. 1, second) and checks
* registers CPBOOT and use them to continue the boot process.
* Make sure the startup code for first core is
* appropriate and shareable with the second core!
*/
SYSCON->CPUCFG |= SYSCON_CPUCFG_CPU1ENABLE_MASK;
/* Boot source for Core 1 from flash */
SYSCON->CPBOOT = SYSCON_CPBOOT_CPBOOT(DT_REG_ADDR(
DT_CHOSEN(zephyr_code_cpu1_partition)));
temp = SYSCON->CPUCTRL;
temp |= 0xc0c48000;
SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CPU1RSTEN_MASK |
SYSCON_CPUCTRL_CPU1CLKEN_MASK;
SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CPU1CLKEN_MASK) &
(~SYSCON_CPUCTRL_CPU1RSTEN_MASK);
return 0;
}
SYS_INIT(_second_core_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
#endif /*defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_LPC55S69_CPU0)*/
|