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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 | /* * Copyright (c) 2017, Erwin Rol <erwin@erwinrol.com> * * SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; #include <st/f4/stm32f407Xg.dtsi> #include <st/f4/stm32f407z(e-g)tx-pinctrl.dtsi> / { model = "Olimex STM32-E407 board"; compatible = "olimex,stm32-e407"; chosen { zephyr,console = &usart1; zephyr,shell-uart = &usart1; zephyr,sram = &sram0; zephyr,flash = &flash0; zephyr,ccm = &ccm0; }; leds { compatible = "gpio-leds"; green_led_1: led_1 { gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; label = "LED1"; }; }; gpio_keys { compatible = "gpio-keys"; user_button: button { label = "Key"; gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; }; }; aliases { led0 = &green_led_1; sw0 = &user_button; }; }; &clk_hse { clock-frequency = <DT_FREQ_M(12)>; status = "okay"; }; &pll { div-m = <6>; mul-n = <168>; div-p = <2>; div-q = <7>; clocks = <&clk_hse>; status = "okay"; }; &rcc { clocks = <&pll>; clock-frequency = <DT_FREQ_M(168)>; ahb-prescaler = <1>; apb1-prescaler = <4>; apb2-prescaler = <2>; }; &usart1 { pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>; current-speed = <115200>; status = "okay"; }; &usart3 { pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>; current-speed = <115200>; status = "okay"; }; &usart6 { pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>; current-speed = <115200>; status = "okay"; }; &rtc { status = "okay"; }; &rng { status = "okay"; }; /* Only one interface should be enabled at a time: usbotg_fs or usbotg_hs */ usb_otg1: &usbotg_fs { pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>; status = "disabled"; }; usb_otg2: &usbotg_hs { pinctrl-0 = <&usb_otg_hs_dm_pb14 &usb_otg_hs_dp_pb15>; status = "okay"; }; &mac { status = "okay"; pinctrl-0 = <ð_mdc_pc1 ð_rxd0_pc4 ð_rxd1_pc5 ð_ref_clk_pa1 ð_mdio_pa2 ð_col_pa3 ð_crs_dv_pa7 ð_tx_en_pg11 ð_txd0_pg13 ð_txd1_pg14>; }; |