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* Copyright (c) 2019 Linaro Ltd.
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pwm/pwm.h>
/ {
chosen {
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
soc {
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
interrupts = <41 0>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
prescaler = <32768>;
status = "disabled";
label = "RTC_0";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <48 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <49 0>;
status = "disabled";
label = "UART_5";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 0>;
status = "disabled";
label = "SPI_1";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 0>;
status = "disabled";
label = "SPI_2";
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
pinctrl: pin-controller@40020000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40020000 0x2000>;
gpioa: gpio@40020000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
label = "GPIOA";
};
gpiob: gpio@40020400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
label = "GPIOB";
};
gpioc: gpio@40020800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
label = "GPIOC";
};
gpiod: gpio@40020c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
label = "GPIOD";
};
gpioe: gpio@40021000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
label = "GPIOE";
};
gpioh: gpio@40021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
label = "GPIOH";
};
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
label = "IWDG";
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
interrupts = <0 7>;
status = "disabled";
label = "WWDG";
};
rcc: rcc@40023800 {
compatible = "st,stm32-rcc";
#clock-cells = <2>;
reg = <0x40023800 0x400>;
label = "STM32_CLK_RCC";
};
flash: flash-controller@40023c00 {
compatible = "st,stm32-flash-controller", "st,stm32l1-flash-controller";
label = "FLASH_CTRL";
reg = <0x40023c00 0x400>;
interrupts = <4 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "soc-nv-flash";
label = "FLASH_STM32";
write-block-size = <4>;
};
};
eeprom: eeprom@8080000{
compatible = "st,stm32-eeprom";
status = "disabled";
label = "EEPROM_0";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
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