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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 | /* * Copyright (c) 2019, Synopsys, Inc. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 */ #include "skeleton.dtsi" #include <dt-bindings/i2c/i2c.h> #include <dt-bindings/gpio/gpio.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "snps,archs38"; reg = <0>; }; cpu@1 { device_type = "cpu"; compatible = "snps,archs38"; reg = <1>; }; cpu@2 { device_type = "cpu"; compatible = "snps,archs38"; reg = <2>; }; cpu@3 { device_type = "cpu"; compatible = "snps,archs38"; reg = <3>; }; }; intc: arcv2-intc { compatible = "snps,arcv2-intc"; interrupt-controller; #interrupt-cells = <2>; }; idu_intc: idu-interrupt-controller { compatible = "snps,archs-idu-intc"; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&intc>; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; interrupt-parent = <&idu_intc>; ranges; ddr0: memory@90000000 { device_type = "memory"; reg = <0x90000000 0x50000000>; }; uart0: uart@f0005000 { compatible = "ns16550"; clock-frequency = <33333333>; reg = <0xf0005000 0x1000>; label = "UART_0"; interrupts = <30 1>; }; uart1: uart@f0026000{ compatible = "ns16550"; clock-frequency = <33333333>; reg = <0xf0026000 0x1000>; label = "UART_1"; interrupts = <46 1>; status = "disabled"; }; uart2: uart@f0027000 { compatible = "ns16550"; clock-frequency = <33333333>; reg = <0xf0027000 0x1000>; label = "UART_2"; interrupts = <47 1>; status = "disabled"; }; uart3: uart@f0028000 { compatible = "ns16550"; clock-frequency = <33333333>; reg = <0xf0028000 0x1000>; label = "UART_3"; interrupts = <48 1>; status = "disabled"; }; gpio0: gpio@f0003000 { compatible = "snps,designware-gpio"; reg = <0xf0003000 0x1000>; bits = <24>; label = "GPIO_0"; interrupt-parent = <&idu_intc>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; i2c0: i2c@f0023000 { compatible = "snps,designware-i2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0xf0023000 0x1000>; interrupts = <43 1>; label = "I2C_0"; status = "disabled"; }; i2c1: i2c@f0024000 { compatible = "snps,designware-i2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0xf0024000 0x1000>; interrupts = <44 1>; label = "I2C_1"; status = "disabled"; }; i2c2: i2c@f0025000 { compatible = "snps,designware-i2c"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0xf0025000 0x1000>; interrupts = <45 1>; label = "I2C_2"; status = "disabled"; }; spi0: spi@f0020000 { compatible = "snps,designware-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0xf0020000 0x1000>; interrupts = <40 1>; label = "SPI_0"; status = "disabled"; }; spi1: spi@f0021000 { compatible = "snps,designware-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0xf0021000 0x1000>; interrupts = <41 1>; label = "SPI_1"; status = "disabled"; }; spi2: spi@f0022000 { compatible = "snps,designware-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0xf0022000 0x1000>; interrupts = <42 1>; label = "SPI_2"; status = "disabled"; }; }; }; |