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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 | /* * Copyright (c) 2017 Linaro Limited * * SPDX-License-Identifier: Apache-2.0 */ #include <st/l4/stm32l4.dtsi> / { soc { pinctrl: pin-controller@48000000 { gpiod: gpio@48000c00 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48000c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>; label = "GPIOD"; }; gpioe: gpio@48001000 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>; label = "GPIOE"; }; gpiof: gpio@48001400 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>; label = "GPIOF"; }; gpiog: gpio@48001800 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x48001800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>; label = "GPIOG"; }; }; usart3: serial@40004800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>; interrupts = <39 0>; status = "disabled"; label = "UART_3"; }; uart4: serial@40004c00 { compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>; interrupts = <52 0>; status = "disabled"; label = "UART_4"; }; uart5: serial@40005000 { compatible = "st,stm32-uart"; reg = <0x40005000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; interrupts = <53 0>; status = "disabled"; label = "UART_5"; }; i2c2: i2c@40005800 { compatible = "st,stm32-i2c-v2"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; status = "disabled"; label= "I2C_2"; }; spi2: spi@40003800 { compatible = "st,stm32-spi-fifo", "st,stm32-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40003800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>; interrupts = <36 5>; status = "disabled"; label = "SPI_2"; }; spi3: spi@40003c00 { compatible = "st,stm32-spi-fifo", "st,stm32-spi"; #address-cells = <1>; #size-cells = <0>; reg = <0x40003c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>; interrupts = <51 5>; status = "disabled"; label = "SPI_3"; }; timers3: timers@40000400 { compatible = "st,stm32-timers"; reg = <0x40000400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; interrupts = <29 0>; interrupt-names = "global"; status = "disabled"; label = "TIMERS_3"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_3"; #pwm-cells = <3>; }; }; timers4: timers@40000800 { compatible = "st,stm32-timers"; reg = <0x40000800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>; interrupts = <30 0>; interrupt-names = "global"; status = "disabled"; label = "TIMERS_4"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_4"; #pwm-cells = <3>; }; }; timers5: timers@40000c00 { compatible = "st,stm32-timers"; reg = <0x40000c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>; interrupts = <50 0>; interrupt-names = "global"; status = "disabled"; label = "TIMERS_5"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <0>; label = "PWM_5"; #pwm-cells = <3>; }; }; timers8: timers@40013400 { compatible = "st,stm32-timers"; reg = <0x40013400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>; interrupts = <43 0>, <44 0>, <45 0>, <46 0>; interrupt-names = "brk", "up", "trgcom", "cc"; status = "disabled"; label = "TIMERS_8"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_8"; #pwm-cells = <3>; }; }; timers17: timers@40014800 { compatible = "st,stm32-timers"; reg = <0x40014800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>; interrupts = <26 0>; interrupt-names = "global"; status = "disabled"; label = "TIMERS_17"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_17"; #pwm-cells = <3>; }; }; sdmmc1: sdmmc@40012800 { compatible = "st,stm32-sdmmc"; reg = <0x40012800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>; status = "disabled"; label = "SDMMC_1"; }; }; }; |