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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 | /* * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com> * Copyright (c) 2019 ST Microelectronics * Copyright (c) 2019 Centaur Analytics, Inc * Copyright (C) 2020 Framework Computer LLC <ktl@frame.work> * * SPDX-License-Identifier: Apache-2.0 */ #include <arm/armv6-m.dtsi> #include <dt-bindings/clock/stm32_clock.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/i2c/i2c.h> #include <dt-bindings/pwm/pwm.h> / { chosen { zephyr,flash-controller = &flash; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m0+"; reg = <0>; }; }; sram0: memory@20000000 { compatible = "mmio-sram"; }; soc { flash: flash-controller@40022000 { compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller"; label = "FLASH_CTRL"; reg = <0x40022000 0x400>; interrupts = <3 0>; #address-cells = <1>; #size-cells = <1>; flash0: flash@8000000 { compatible = "soc-nv-flash"; label = "FLASH_STM32"; write-block-size = <8>; erase-block-size = <2048>; }; }; rcc: rcc@40021000 { compatible = "st,stm32-rcc"; #clock-cells = <2>; reg = <0x40021000 0x400>; label = "STM32_CLK_RCC"; }; pinctrl: pin-controller@50000000 { compatible = "st,stm32-pinmux"; #address-cells = <1>; #size-cells = <1>; reg = <0x50000000 0x2000>; gpioa: gpio@50000000 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x50000000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>; label = "GPIOA"; }; gpiob: gpio@50000400 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x50000400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>; label = "GPIOB"; }; gpioc: gpio@50000800 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x50000800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>; label = "GPIOC"; }; gpiod: gpio@50000c00 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x50000c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>; label = "GPIOD"; }; gpiof: gpio@50001400 { compatible = "st,stm32-gpio"; gpio-controller; #gpio-cells = <2>; reg = <0x50001400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>; label = "GPIOF"; }; }; iwdg: watchdog@40003000 { compatible = "st,stm32-watchdog"; reg = <0x40003000 0x400>; label = "IWDG"; status = "disabled"; }; wwdg: watchdog@40002c00 { compatible = "st,stm32-window-watchdog"; reg = <0x40002C00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>; label = "WWDG"; interrupts = <0 7>; status = "disabled"; }; lpuart1: serial@40008000 { compatible = "st,stm32-lpuart", "st,stm32-uart"; reg = <0x40008000 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>; interrupts = <29 3>; interrupt-names = "combined"; status = "disabled"; label = "LPUART_1"; }; usart1: serial@40013800 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40013800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>; interrupts = <27 0>; status = "disabled"; label = "UART_1"; }; usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>; interrupts = <28 0>; status = "disabled"; label = "UART_2"; }; timers3: timers@40000400 { compatible = "st,stm32-timers"; reg = <0x40000400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>; interrupts = <16 0>; interrupt-names = "global"; status = "disabled"; label = "TIMERS_3"; pwm { compatible = "st,stm32-pwm"; status = "disabled"; st,prescaler = <10000>; label = "PWM_3"; #pwm-cells = <3>; }; }; i2c1: i2c@40005400 { compatible = "st,stm32-i2c-v2"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005400 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>; interrupts = <23 0>; interrupt-names = "combined"; status = "disabled"; label = "I2C_1"; }; i2c2: i2c@40005800 { compatible = "st,stm32-i2c-v2"; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40005800 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>; interrupts = <24 0>; interrupt-names = "combined"; status = "disabled"; label = "I2C_2"; }; }; }; &nvic { arm,num-irq-priority-bits = <2>; }; |