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* Copyright (c) 2018, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/rdc/imx_rdc.h>
/ {
aliases {
epit-1 = &epit1;
epit-2 = &epit2;
gpio-1 = &gpio1;
gpio-2 = &gpio2;
gpio-3 = &gpio3;
gpio-4 = &gpio4;
gpio-5 = &gpio5;
gpio-6 = &gpio6;
gpio-7 = &gpio7;
mu-b = &mub;
uart-1 = &uart1;
uart-2 = &uart2;
uart-3 = &uart3;
uart-4 = &uart4;
uart-5 = &uart5;
uart-6 = &uart6;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
status = "disabled";
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <1>;
};
};
tcml:memory@1fff8000 {
compatible = "nxp,imx-itcm";
reg = <0x1fff8000 0x00008000>;
label = "TCML";
};
tcmu:memory@20000000 {
compatible = "nxp,imx-dtcm";
reg = <0x20000000 0x00008000>;
label = "TCMU";
};
ocram_s:memory@208f8000 {
device_type = "memory";
compatible = "nxp,imx-sys-bus";
reg = <0x208f8000 0x00004000>;
label = "OCRAM_S";
};
ocram:memory@20900000 {
device_type = "memory";
compatible = "nxp,imx-sys-bus";
reg = <0x20900000 0x00020000>;
label = "OCRAM";
};
ddr:memory@80000000 {
device_type = "memory";
compatible = "nxp,imx-sys-bus";
reg = <0x80000000 0x60000000>;
label = "DDR";
};
flash:memory@DT_FLASH_ADDR {
compatible = "soc-nv-flash";
reg = <DT_FLASH_ADDR DT_FLASH_SIZE>;
};
sram:memory@DT_SRAM_ADDR {
reg = <DT_SRAM_ADDR DT_SRAM_SIZE>;
};
soc {
uart1:uart@42020000 {
compatible = "nxp,imx-uart";
reg = <0x42020000 0x00004000>;
interrupts = <26 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_1";
status = "disabled";
};
uart2:uart@421e8000 {
compatible = "nxp,imx-uart";
reg = <0x421e8000 0x00004000>;
interrupts = <27 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_2";
status = "disabled";
};
uart3:uart@421ec000 {
compatible = "nxp,imx-uart";
reg = <0x421ec000 0x00004000>;
interrupts = <28 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_3";
status = "disabled";
};
uart4:uart@421f0000 {
compatible = "nxp,imx-uart";
reg = <0x421f0000 0x00004000>;
interrupts = <29 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_4";
status = "disabled";
};
uart5:uart@421f4000 {
compatible = "nxp,imx-uart";
reg = <0x421f4000 0x00004000>;
interrupts = <30 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_5";
status = "disabled";
};
uart6:uart@422a0000 {
compatible = "nxp,imx-uart";
reg = <0x422a0000 0x00004000>;
interrupts = <17 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "UART_6";
status = "disabled";
};
gpio1:gpio@4209c000 {
compatible = "nxp,imx-gpio";
reg = <0x4209c000 0x4000>;
interrupts = <66 0>, <67 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio2:gpio@420a0000 {
compatible = "nxp,imx-gpio";
reg = <0x420a0000 0x4000>;
interrupts = <68 0>, <69 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio3:gpio@420a4000 {
compatible = "nxp,imx-gpio";
reg = <0x420a4000 0x4000>;
interrupts = <70 0>, <71 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio4:gpio@420a8000 {
compatible = "nxp,imx-gpio";
reg = <0x420a8000 0x4000>;
interrupts = <72 0>, <73 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio5:gpio@420ac000 {
compatible = "nxp,imx-gpio";
reg = <0x420ac000 0x4000>;
interrupts = <74 0>, <75 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_5";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio6:gpio@420b0000 {
compatible = "nxp,imx-gpio";
reg = <0x420b0000 0x4000>;
interrupts = <76 0>, <77 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_6";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
gpio7:gpio@420b4000 {
compatible = "nxp,imx-gpio";
reg = <0x420b4000 0x4000>;
interrupts = <78 0>, <79 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "GPIO_7";
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
mub:mu@4229c000 {
compatible = "nxp,imx-mu";
reg = <0x4229c000 0x4000>;
interrupts = <99 0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "MU_B";
status = "disabled";
};
epit1:epit@420d0000 {
compatible = "nxp,imx-epit";
reg = <0x420d0000 0x4000>;
interrupts = <56 0>;
prescaler = <0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "EPIT_1";
status = "disabled";
};
epit2:epit@420d4000 {
compatible = "nxp,imx-epit";
reg = <0x420d4000 0x4000>;
interrupts = <57 0>;
prescaler = <0>;
rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW)|\
RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
RDC_DOMAIN_PERM_RW))>;
label = "EPIT_2";
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
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