Loading...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 | /* SPDX-License-Identifier: Apache-2.0 */
/dts-v1/;
#include <arm/armv7-m.dtsi>
/ {
compatible = "arm,beetle";
#address-cells = <1>;
#size-cells = <1>;
aliases {
watchdog0 = &wdog0;
};
chosen {
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-m3";
clock-frequency = <24000000>;
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 0x20000>;
};
flash0: flash@0 {
compatible = "soc-nv-flash";
reg = <0 0x40000>;
};
sysclk: system-clock {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
soc {
timer0: timer@40000000 {
compatible = "arm,cmsdk-timer";
reg = <0x40000000 0x1000>;
interrupts = <8 3>;
label = "TIMER_0";
};
timer1: timer@40001000 {
compatible = "arm,cmsdk-timer";
reg = <0x40001000 0x1000>;
interrupts = <9 3>;
label = "TIMER_1";
};
dtimer0: dtimer@40002000 {
compatible = "arm,cmsdk-dtimer";
reg = <0x40002000 0x1000>;
interrupts = <10 3>;
label = "DTIMER_0";
};
uart0: uart@40004000 {
compatible = "arm,cmsdk-uart";
reg = <0x40004000 0x1000>;
interrupts = <0 3>;
clocks = <&sysclk>;
current-speed = <115200>;
label = "UART_0";
};
uart1: uart@40005000 {
compatible = "arm,cmsdk-uart";
reg = <0x40005000 0x1000>;
interrupts = <2 3>;
clocks = <&sysclk>;
current-speed = <115200>;
label = "UART_1";
};
wdog0: wdog@40008000 {
compatible = "arm,cmsdk-watchdog";
clocks = <&sysclk>;
reg = <0x40008000 0x1000>;
label = "WATCHDOG";
};
gpio0: gpio@40010000 {
compatible = "arm,cmsdk-gpio";
reg = <0x40010000 0x1000>;
interrupts = <6 3>;
gpio-controller;
#gpio-cells = <2>;
label = "GPIO_0";
};
gpio1: gpio@40011000 {
compatible = "arm,cmsdk-gpio";
reg = <0x40011000 0x1000>;
interrupts = <7 3>;
gpio-controller;
#gpio-cells = <2>;
label = "GPIO_1";
};
gpio2: gpio@40012000 {
compatible = "arm,cmsdk-gpio";
reg = <0x40012000 0x1000>;
interrupts = <42 3>;
gpio-controller;
#gpio-cells = <2>;
label = "GPIO_2";
};
gpio3: gpio@40013000 {
compatible = "arm,cmsdk-gpio";
reg = <0x40013000 0x1000>;
interrupts = <43 3>;
gpio-controller;
#gpio-cells = <2>;
label = "GPIO_3";
};
};
};
&nvic {
arm,num-irq-priority-bits = <3>;
};
|