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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 | /* * Copyright (c) 2019 Nordic Semiconductor ASA * * SPDX-License-Identifier: Apache-2.0 */ #include <arm/armv8-m.dtsi> #include <dt-bindings/i2c/i2c.h> #include <dt-bindings/gpio/gpio.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m33f"; reg = <0>; #address-cells = <1>; #size-cells = <1>; mpu: mpu@e000ed90 { compatible = "arm,armv8m-mpu"; reg = <0xe000ed90 0x40>; arm,num-mpu-regions = <16>; }; }; }; aliases { flash-controller = &flash_controller; rtc-0 = &rtc0; rtc-1 = &rtc1; uart-0 = &uart0; uart-1 = &uart1; uart-2 = &uart2; uart-3 = &uart3; adc-0 = &adc; egu-0 = &egu0; egu-1 = &egu1; egu-2 = &egu2; egu-3 = &egu3; egu-4 = &egu4; egu-5 = &egu5; gpio-0 = &gpio0; gpio-1 = &gpio1; gpiote-0 = &gpiote; i2c-0 = &i2c0; i2c-1 = &i2c1; i2c-2 = &i2c2; i2c-3 = &i2c3; ipc-0 = &ipc; pdm-0 = &pdm0; spi-0 = &spi0; spi-1 = &spi1; spi-2 = &spi2; spi-3 = &spi3; spi-4 = &spi4; pwm-0 = &pwm0; pwm-1 = &pwm1; pwm-2 = &pwm2; pwm-3 = &pwm3; wdt-0 = &wdt; timer-0 = &timer0; timer-1 = &timer1; timer-2 = &timer2; }; chosen { zephyr,flash-controller = &flash_controller; }; soc { sram0: memory@20000000 { device_type = "memory"; compatible = "mmio-sram"; }; peripheral@50000000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x50000000 0x10000000>; /* Common nRF5340 Application MCU * peripheral description */ #include "nrf5340_cpuapp_common.dtsi" }; /* Additional Secure peripherals */ cryptocell: crypto@50844000 { compatible = "nordic,nrf-cc312"; reg = <0x50844000 0x1000>; label = "CRYPTOCELL"; status = "okay"; #address-cells = <1>; #size-cells = <1>; cryptocell312: crypto@50845000 { compatible = "arm,cryptocell-312"; reg = <0x50845000 0x1000>; interrupts = <68 1>; label = "CRYPTOCELL312"; }; }; gpiote: gpiote@5000d000 { compatible = "nordic,nrf-gpiote"; reg = <0x5000d000 0x1000>; interrupts = <13 5>; status = "disabled"; label = "GPIOTE_0"; }; spu: spu@50003000 { compatible = "nordic,nrf-spu"; reg = <0x50003000 0x1000>; interrupts = <3 1>; status = "okay"; }; ficr: ficr@ff0000 { compatible = "nordic,nrf-ficr"; reg = <0xff0000 0x1000>; status = "okay"; }; uicr: uicr@ff8000 { compatible = "nordic,nrf-uicr"; reg = <0xff8000 0x1000>; status = "okay"; }; }; }; &nvic { arm,num-irq-priority-bits = <3>; }; |