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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 | /* * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com> * * SPDX-License-Identifier: Apache-2.0 */ /** * @file * @brief Cortex-A public interrupt handling * * ARM64-specific kernel interrupt handling interface. * Included by arm/aarch64/arch.h. */ #ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_IRQ_H_ #define ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_IRQ_H_ #include <irq.h> #include <sw_isr_table.h> #include <stdbool.h> #ifdef __cplusplus extern "C" { #endif #ifdef _ASMLANGUAGE GTEXT(arch_irq_enable) GTEXT(arch_irq_disable) GTEXT(arch_irq_is_enabled) #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) GTEXT(z_soc_irq_get_active) GTEXT(z_soc_irq_eoi) #endif /* CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ #else #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) extern void arch_irq_enable(unsigned int irq); extern void arch_irq_disable(unsigned int irq); extern int arch_irq_is_enabled(unsigned int irq); /* internal routine documented in C file, needed by IRQ_CONNECT() macro */ extern void z_arm64_irq_priority_set(unsigned int irq, unsigned int prio, u32_t flags); #else /* * When a custom interrupt controller is specified, map the architecture * interrupt control functions to the SoC layer interrupt control functions. */ void z_soc_irq_init(void); void z_soc_irq_enable(unsigned int irq); void z_soc_irq_disable(unsigned int irq); int z_soc_irq_is_enabled(unsigned int irq); void z_soc_irq_priority_set( unsigned int irq, unsigned int prio, unsigned int flags); unsigned int z_soc_irq_get_active(void); void z_soc_irq_eoi(unsigned int irq); #define arch_irq_enable(irq) z_soc_irq_enable(irq) #define arch_irq_disable(irq) z_soc_irq_disable(irq) #define arch_irq_is_enabled(irq) z_soc_irq_is_enabled(irq) #define z_arm64_irq_priority_set(irq, prio, flags) \ z_soc_irq_priority_set(irq, prio, flags) #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */ extern void z_arm64_interrupt_init(void); /* All arguments must be computable by the compiler at build time. * * Z_ISR_DECLARE will populate the .intList section with the interrupt's * parameters, which will then be used by gen_irq_tables.py to create * the vector table and the software ISR table. This is all done at * build-time. * * We additionally set the priority in the interrupt controller at * runtime. */ #define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \ { \ Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \ z_arm64_irq_priority_set(irq_p, priority_p, flags_p); \ } #define ARCH_IRQ_DIRECT_CONNECT(irq_p, priority_p, isr_p, flags_p) \ { \ Z_ISR_DECLARE(irq_p, ISR_FLAG_DIRECT, isr_p, NULL); \ z_arm64_irq_priority_set(irq_p, priority_p, flags_p); \ } /* Spurious interrupt handler. Throws an error if called */ extern void z_irq_spurious(void *unused); #ifdef CONFIG_GEN_SW_ISR_TABLE /* Architecture-specific common entry point for interrupts from the vector * table. Most likely implemented in assembly. Looks up the correct handler * and parameter from the _sw_isr_table and executes it. */ extern void _isr_wrapper(void); #endif #endif /* _ASMLANGUAGE */ #ifdef __cplusplus } #endif #endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH64_IRQ_H_ */ |