Linux Audio

Check our new training course

Open Menu / soc / xtensa / intel_s1000 / dts_fixup.h
Loading...
  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
/* SPDX-License-Identifier: Apache-2.0 */

/* SoC level DTS fixup file */

#define DT_CPU_CLOCK_FREQUENCY DT_CADENCE_TENSILICA_XTENSA_LX6_0_CLOCK_FREQUENCY

#define DT_UART_NS16550_PORT_0_BASE_ADDR	DT_NS16550_80800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_BAUD_RATE	DT_NS16550_80800_CURRENT_SPEED
#define DT_UART_NS16550_PORT_0_NAME		DT_NS16550_80800_LABEL
#define DT_UART_NS16550_PORT_0_IRQ		DT_NS16550_80800_IRQ_0
#define DT_UART_NS16550_PORT_0_IRQ_PRI		DT_NS16550_80800_IRQ_0_PRIORITY
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS	DT_NS16550_80800_IRQ_0_SENSE
#define DT_UART_NS16550_PORT_0_CLK_FREQ	DT_NS16550_80800_CLOCK_FREQUENCY

#define DT_L2_SRAM_BASE				CONFIG_SRAM_BASE_ADDRESS
#define DT_L2_SRAM_SIZE				CONFIG_SRAM_SIZE * 1024

#define DT_LP_SRAM_BASE				DT_INST_1_MMIO_SRAM_BASE_ADDRESS
#define DT_LP_SRAM_SIZE				DT_INST_1_MMIO_SRAM_SIZE

#define DT_CAVS_ICTL_BASE_ADDR			DT_INTEL_CAVS_INTC_78800_BASE_ADDRESS
#define DT_CAVS_ICTL_0_IRQ				DT_INTEL_CAVS_INTC_78800_IRQ_0
#define DT_CAVS_ICTL_0_IRQ_PRI		DT_INTEL_CAVS_INTC_78800_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_0_IRQ_FLAGS			DT_INTEL_CAVS_INTC_78800_IRQ_0_SENSE

#define DT_CAVS_ICTL_1_IRQ				DT_INTEL_CAVS_INTC_78810_IRQ_0
#define DT_CAVS_ICTL_1_IRQ_PRI		DT_INTEL_CAVS_INTC_78810_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_1_IRQ_FLAGS			DT_INTEL_CAVS_INTC_78810_IRQ_0_SENSE

#define DT_CAVS_ICTL_2_IRQ				DT_INTEL_CAVS_INTC_78820_IRQ_0
#define DT_CAVS_ICTL_2_IRQ_PRI		DT_INTEL_CAVS_INTC_78820_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_2_IRQ_FLAGS			DT_INTEL_CAVS_INTC_78820_IRQ_0_SENSE

#define DT_CAVS_ICTL_3_IRQ				DT_INTEL_CAVS_INTC_78830_IRQ_0
#define DT_CAVS_ICTL_3_IRQ_PRI		DT_INTEL_CAVS_INTC_78830_IRQ_0_PRIORITY
#define DT_CAVS_ICTL_3_IRQ_FLAGS			DT_INTEL_CAVS_INTC_78830_IRQ_0_SENSE

#define DT_INTC_DW_0_BASE_ADDR		\
	DT_SNPS_DESIGNWARE_INTC_81800_BASE_ADDRESS
#define DT_INTC_DW_0_NAME		DT_SNPS_DESIGNWARE_INTC_81800_LABEL
#define DT_INTC_DW_0_IRQ		DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0
#define DT_INTC_DW_0_IRQ_PRI		\
	DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_PRIORITY
#define DT_INTC_DW_0_IRQ_FLAGS		\
	DT_SNPS_DESIGNWARE_INTC_81800_IRQ_0_SENSE
#define DT_INTC_DW_0_NUM_IRQS		DT_SNPS_DESIGNWARE_INTC_81800_NUM_IRQS

#define DT_SPI_DW_0_BASE_ADDRESS		\
	DT_SNPS_DESIGNWARE_SPI_E000_BASE_ADDRESS
#define DT_SPI_DW_0_CLOCK_FREQUENCY		\
	DT_SNPS_DESIGNWARE_SPI_E000_CLOCKS_CLOCK_FREQUENCY
#define DT_SPI_DW_0_NAME			\
	DT_SNPS_DESIGNWARE_SPI_E000_LABEL
#define DT_SPI_DW_0_IRQ				\
	DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0
#define DT_SPI_DW_0_IRQ_FLAGS			\
	DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_SENSE
#define DT_SPI_DW_0_IRQ_PRI			\
	DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY

#define DT_GPIO_DW_0_BASE_ADDR		\
	DT_SNPS_DESIGNWARE_GPIO_80C00_BASE_ADDRESS
#define DT_GPIO_DW_0_BITS		\
	DT_SNPS_DESIGNWARE_GPIO_80C00_BITS
#define DT_GPIO_DW_0_IRQ		\
	DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0
#define CONFIG_GPIO_DW_0_IRQ_PRI	\
	DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_IRQ_FLAGS		0
#define CONFIG_GPIO_DW_0_NAME		\
	DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL

#define DT_PINMUX_BASE_ADDR		\
	DT_INTEL_S1000_PINMUX_81C30_BASE_ADDRESS
#define DT_PINMUX_CTRL_REG_COUNT	\
	(DT_INTEL_S1000_PINMUX_81C30_SIZE / 4)

#define DT_DMA_DW_0_NAME		DT_SNPS_DESIGNWARE_DMA_7C000_LABEL
#define DT_DMA_DW_0_BASE_ADDR				\
	DT_SNPS_DESIGNWARE_DMA_7C000_BASE_ADDRESS
#define DT_DMA_DW_0_IRQ			DT_SNPS_DESIGNWARE_DMA_7C000_IRQ_0
#define DT_DMA_DW_0_IRQ_PRI				\
	DT_SNPS_DESIGNWARE_DMA_7C000_IRQ_0_PRIORITY
#define DT_DMA_DW_0_IRQ_FLAGS				\
	DT_SNPS_DESIGNWARE_DMA_7C000_IRQ_0_SENSE

#define DT_DMA_DW_1_NAME		DT_SNPS_DESIGNWARE_DMA_7D000_LABEL
#define DT_DMA_DW_1_BASE_ADDR				\
	DT_SNPS_DESIGNWARE_DMA_7D000_BASE_ADDRESS
#define DT_DMA_DW_1_IRQ			DT_SNPS_DESIGNWARE_DMA_7D000_IRQ_0
#define DT_DMA_DW_1_IRQ_PRI				\
	DT_SNPS_DESIGNWARE_DMA_7D000_IRQ_0_PRIORITY
#define DT_DMA_DW_1_IRQ_FLAGS				\
	DT_SNPS_DESIGNWARE_DMA_7D000_IRQ_0_SENSE

#define DT_DMA_DW_2_NAME		DT_SNPS_DESIGNWARE_DMA_7E000_LABEL
#define DT_DMA_DW_2_BASE_ADDR				\
	DT_SNPS_DESIGNWARE_DMA_7E000_BASE_ADDRESS
#define DT_DMA_DW_2_IRQ			DT_SNPS_DESIGNWARE_DMA_7E000_IRQ_0
#define DT_DMA_DW_2_IRQ_PRI				\
	DT_SNPS_DESIGNWARE_DMA_7E000_IRQ_0_PRIORITY
#define DT_DMA_DW_2_IRQ_FLAGS				\
	DT_SNPS_DESIGNWARE_DMA_7E000_IRQ_0_SENSE

/*
 * USB configuration
 */
#define DT_USB_DW_0_BASE_ADDRESS	\
	DT_SNPS_DESIGNWARE_USB_A0000_BASE_ADDRESS
#define DT_USB_DW_0_NAME		DT_SNPS_DESIGNWARE_USB_A0000_LABEL
#define DT_USB_DW_0_IRQ			DT_SNPS_DESIGNWARE_USB_A0000_IRQ_0
#define DT_USB_DW_0_IRQ_PRI		\
	DT_SNPS_DESIGNWARE_USB_A0000_IRQ_0_PRIORITY
#define DT_USB_DW_0_IRQ_FLAGS		\
	DT_SNPS_DESIGNWARE_USB_A0000_IRQ_0_SENSE

/* End of SoC Level DTS fixup file */