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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 | /* * Copyright (c) 2017, NXP * * SPDX-License-Identifier: Apache-2.0 */ #include <dt-bindings/gpio/gpio.h> / { aliases{ gpio-0 = &gpio0; gpio-1 = &gpio1; mailbox-0 = &mailbox0; spi-5 = &spi5; usart-0 = &usart0; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-m4f"; reg = <0>; }; cpu1: cpu@1 { compatible = "arm,cortex-m0+"; reg = <1>; }; }; sram0:memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 0x10000>; }; sram1:memory@20010000 { compatible = "mmio-sram"; reg = <0x20010000 0x10000>; }; sram2:memory@20020000 { compatible = "mmio-sram"; reg = <0x20020000 0x8000>; }; sramx:memory@40000000{ compatible = "mmio-sram"; reg = <0x40000000 0x8000>; }; soc { flash0:flash@0 { compatible = "soc-nv-flash"; reg = <0 0x40000>; }; usart0:usart@40086000 { compatible = "nxp,lpc-usart"; reg = <0x40086000 0xE44>; interrupts = <14 0>; label = "USART_0"; status = "disabled"; }; gpio0: gpio@0 { compatible = "nxp,lpc-gpio"; reg = <0x4008c000 0x2488>; interrupts = <4 2>,<5 2>,<6 2>,<7 2>; label = "GPIO_0"; gpio-controller; #gpio-cells = <2>; }; gpio1: gpio@1 { compatible = "nxp,lpc-gpio"; reg = <0x4008C000 0x2488>; interrupts = <32 2>,<33 2>,<34 2>,<35 2>; label = "GPIO_1"; gpio-controller; #gpio-cells = <2>; }; mailbox0:mailbox@4008b000 { compatible = "nxp,lpc-mailbox"; reg = <0x4008b000 0xEC>; interrupts = <31 0>; label = "MAILBOX_0"; status = "disabled"; }; spi5: spi@40096000 { compatible = "nxp,lpc-spi"; reg = <0x40096000 0x1000>; interrupts = <19 0>; label = "SPI_5"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; }; }; &nvic { arm,num-irq-priority-bits = <3>; }; |