/*
 * Copyright (c) 2019 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* .dtsi header for nRF5340 CPUAPP (Application MCU), Non-Secure domain */

#include <arm/armv8-m.dtsi>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m33f";
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv8m-mpu";
				reg = <0xe000ed90 0x40>;
				arm,num-mpu-regions = <16>;
			};
		};
	};

	aliases {
		flash-controller = &flash_controller;
		rtc-0 = &rtc0;
		rtc-1 = &rtc1;
		uart-0 = &uart0;
		uart-1 = &uart1;
		uart-2 = &uart2;
		uart-3 = &uart3;
		adc-0 = &adc;
		gpio-0 = &gpio0;
		gpio-1 = &gpio1;
		gpiote-0 = &gpiote;
		i2c-0 = &i2c0;
		i2c-1 = &i2c1;
		i2c-2 = &i2c2;
		i2c-3 = &i2c3;
		spi-0 = &spi0;
		spi-1 = &spi1;
		spi-2 = &spi2;
		spi-3 = &spi3;
		spi-4 = &spi4;
		pwm-0 = &pwm0;
		pwm-1 = &pwm1;
		pwm-2 = &pwm2;
		pwm-3 = &pwm3;
		wdt-0 = &wdt;
		timer-0 = &timer0;
		timer-1 = &timer1;
		timer-2 = &timer2;
	};

	soc {
		sram0: memory@20000000 {
			device_type = "memory";
			compatible = "mmio-sram";
		};

		peripheral@40000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x40000000 0x10000000>;

			/* Common nRF5340 Application MCU
			 * peripheral description
			 */
			#include "nrf5340_cpuapp_common.dtsi"
		};

		/* Additional Non-Secure peripherals */
		gpiote: gpiote@4002f000 {
			compatible = "nordic,nrf-gpiote";
			reg = <0x4002f000 0x1000>;
			interrupts = <47 5>;
			status = "disabled";
			label = "GPIOTE_1";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};