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/* * Copyright (c) 2017 Intel Corporation. * * SPDX-License-Identifier: Apache-2.0 */ #include "skeleton.dtsi" #include <dt-bindings/interrupt-controller/intel-ioapic.h> / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "qemu32"; reg = <0>; }; }; intc: ioapic@fec00000 { compatible = "intel,ioapic"; reg = <0xfec00000 0x1000>; interrupt-controller; #interrupt-cells = <3>; }; sram0: memory@100000 { device_type = "memory"; compatible = "mmio-sram"; reg = <0x00100000 DT_SRAM_SIZE>; }; soc { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; ranges; uart0: uart@3f8 { compatible = "ns16550"; reg = <0x000003f8 0x100>; label = "UART_0"; clock-frequency = <1843200>; interrupts = <4 IRQ_TYPE_EDGE_RISING 3>; interrupt-parent = <&intc>; status = "disabled"; }; uart1: uart@2f8 { compatible = "ns16550"; reg = <0x000002f8 0x100>; label = "UART_1"; clock-frequency = <1843200>; interrupts = <3 IRQ_TYPE_EDGE_RISING 3>; interrupt-parent = <&intc>; status = "disabled"; }; hpet: hpet@fed00000 { label = "HPET"; compatible = "intel,hpet"; reg = <0xfed00000 0x400>; interrupts = <2 IRQ_TYPE_EDGE_RISING 4>; interrupt-parent = <&intc>; status = "disabled"; }; }; }; |