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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 | /* SPDX-License-Identifier: Apache-2.0 */ #include <arm/armv7-m.dtsi> #include <dt-bindings/i2c/i2c.h> #include <dt-bindings/gpio/gpio.h> #define INT_UARTA0 21 // UART0 Rx and Tx #define INT_UARTA1 22 // UART1 Rx and Tx #define INT_I2CA0 24 // I2C controller /* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */ /* which are offset by 16: */ #define EXP_UARTA0 (INT_UARTA0 - 16) #define EXP_UARTA1 (INT_UARTA1 - 16) #define EXP_I2CA0 (INT_I2CA0 - 16) #define EXC_GPIOA0 0 /* (INT_GPIOA0 - 16) = (16-16) */ #define EXC_GPIOA1 1 /* (INT_GPIOA1 - 16) = (17-16) */ #define EXC_GPIOA2 2 /* (INT_GPIOA2 - 16) = (18-16) */ #define EXC_GPIOA3 3 /* (INT_GPIOA3 - 16) = (19-16) */ / { cpus { #address-cells = <1>; #size-cells = <0>; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-m4"; reg = <0>; }; }; sram0: memory@20000000 { compatible = "mmio-sram"; }; flash0: serial-flash@0 { compatible = "serial-flash"; }; sysclk: system-clock { compatible = "fixed-clock"; clock-frequency = <80000000>; #clock-cells = <0>; }; soc { uart0: uart@4000c000 { compatible = "ti,cc32xx-uart"; reg = <0x4000c000 0x4c>; interrupts = <EXP_UARTA0 3>; clocks = <&sysclk>; status = "disabled"; label = "UART_0"; }; uart1: uart@4000d000 { compatible = "ti,cc32xx-uart"; reg = <0x4000d000 0x4c>; interrupts = <EXP_UARTA1 3>; clocks = <&sysclk>; status = "disabled"; label = "UART_1"; }; i2c0: i2c@40020000 { compatible = "ti,cc32xx-i2c"; clocks = <&sysclk>; clock-frequency = <I2C_BITRATE_STANDARD>; #address-cells = <1>; #size-cells = <0>; reg = <0x40020000 0xfc8>; interrupts = <EXP_I2CA0 3>; status = "disabled"; label= "I2C_0"; }; gpioa0: gpio@40004000 { compatible = "ti,cc32xx-gpio"; reg = <0x40004000 0x1000>; interrupts = <0 1>; label = "GPIO_A0"; gpio-controller; #gpio-cells = <2>; }; gpioa1: gpio@40005000 { compatible = "ti,cc32xx-gpio"; reg = <0x40005000 0x1000>; interrupts = <1 1>; label = "GPIO_A1"; gpio-controller; #gpio-cells = <2>; }; gpioa2: gpio@40006000 { compatible = "ti,cc32xx-gpio"; reg = <0x40006000 0x1000>; interrupts = <2 1>; label = "GPIO_A2"; gpio-controller; #gpio-cells = <2>; }; gpioa3: gpio@40007000 { compatible = "ti,cc32xx-gpio"; reg = <0x40007000 0x1000>; interrupts = <3 1>; label = "GPIO_A3"; gpio-controller; #gpio-cells = <2>; }; }; }; &nvic { arm,num-irq-priority-bits = <3>; }; |