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Elixir Cross Referencer

# interrupt controller configuration options

# Copyright (c) 2015 Intel Corporation
# SPDX-License-Identifier: Apache-2.0

menu "Interrupt Controllers"

menuconfig LOAPIC
	bool "LOAPIC"
	depends on X86
	help
	  This option selects local APIC as the interrupt controller.
if LOAPIC
config LOAPIC_BASE_ADDRESS
	hex "Local APIC Base Address"
	default 0xFEE00000
	help
	  This option specifies the base address of the Local APIC device.

config X2APIC
	bool "Access local APIC in x2APIC mode"
	default n
	help
	  If your local APIC supports x2APIC mode, turn this on.

config LOAPIC_SPURIOUS_VECTOR
	bool "Handle LOAPIC spurious interrupts"
	help
	  A special situation may occur when a processor raises its task
	  priority to be greater than or equal to the level of the
	  interrupt for which the processor INTR signal is currently being
	  asserted. If at the time the INTA cycle is issued, the
	  interrupt that was to be dispensed has become masked (programmed
	  by software), the local APIC will deliver a spurious-interrupt
	  vector. Dispensing the spurious-interrupt vector does not affect
	  the ISR, so the handler for this vector should return without an EOI.
	  From x86 manual Volume 3 Section 10.9.

config LOAPIC_SPURIOUS_VECTOR_ID
	int "LOAPIC spurious vector ID"
	default -1
	depends on LOAPIC_SPURIOUS_VECTOR
	help
	  IDT vector to use for spurious LOAPIC interrupts. Note that some
	  arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF.
	  If this value is left at -1 the last entry in the IDT will be used.

config IOAPIC
	bool "IO-APIC"
	default y
	help
	  This option signifies that the target has an IO-APIC device. This
	  capability allows IO-APIC-dependent code to be included.

config IOAPIC_NUM_RTES
	int "Number of Redirection Table Entries available"
	default 24
	depends on IOAPIC
	help
	  This option indicates the maximum number of Redirection Table Entries
	  (RTEs) (one per IRQ available to the IO-APIC) made available to the
	  kernel, regardless of the number provided by the hardware itself. For
	  most efficient usage of memory, it should match the number of IRQ lines
	  needed by devices connected to the IO-APIC.

config IOAPIC_MASK_RTE
	bool "Mask out RTE entries on boot"
	default y
	depends on IOAPIC
	help
	  At boot, mask all IOAPIC RTEs if they may be in an undefined state.
	  You don't need this if the RTEs are either all guaranteed to be masked
	  when the OS starts up, or a previous boot stage has done some IOAPIC
	  configuration that needs to be preserved.

endif # LOAPIC

config ARCV2_INTERRUPT_UNIT
	bool "ARCv2 Interrupt Unit"
	default y
	depends on ARC
	help
	  The ARCv2 interrupt unit has 16 allocated exceptions associated with
	  vectors 0 to 15 and 240 interrupts associated with vectors 16 to 255.
	  The interrupt unit is optional in the ARCv2-based processors. When
	  building a processor, you can configure the processor to include an
	  interrupt unit. The ARCv2 interrupt unit is highly programmable.

config PLIC
	bool "Platform Level Interrupt Controller (PLIC)"
	default y
	depends on SOC_FAMILY_RISCV_PRIVILEGE
	select RISCV_HAS_PLIC
	select MULTI_LEVEL_INTERRUPTS
	select 2ND_LEVEL_INTERRUPTS
	help
	  Platform Level Interrupt Controller provides support
	  for external interrupt lines defined by the RISC-V SoC;

config VEXRISCV_LITEX_IRQ
	bool "VexRiscv LiteX Interrupt controller"
	depends on SOC_RISCV32_LITEX_VEXRISCV
	help
	  IRQ implementation for LiteX VexRiscv

config DW_ICTL
	bool "Designware Interrupt Controller"
	depends on MULTI_LEVEL_INTERRUPTS
	help
	  Designware Interrupt Controller can be used as a 2nd level interrupt
	  controller which combines several sources of interrupt into one line
	  that is then routed to the 1st level interrupt controller.

config DW_ICTL_NAME
	string "Name for Designware Interrupt Controller"
	depends on DW_ICTL
	default "DW_ICTL"
	help
	  Give a name for the instance of Designware Interrupt Controller

config DW_ICTL_OFFSET
	int "Parent interrupt number to which DW_ICTL maps"
	default 0
	depends on DW_ICTL
	help
	  Parent interrupt number to which DW_ICTL maps

config DW_ISR_TBL_OFFSET
	int "Offset in the SW ISR Table"
	default 0
	depends on DW_ICTL
	help
	  This indicates the offset in the SW_ISR_TABLE beginning from where
	  the ISRs for Designware Interrupt Controller are assigned.

config DW_ICTL_INIT_PRIORITY
	int "Init priority for DW interrupt controller"
	default 60
	depends on DW_ICTL
	help
	  DesignWare Interrupt Controller initialization priority.

config GIC
	bool "ARM Generic Interrupt Controller (GIC)"
	depends on CPU_CORTEX_R
	help
	  The ARM Generic Interrupt Controller works with Cortex-A and
	  Cortex-R processors.

source "drivers/interrupt_controller/Kconfig.stm32"

source "drivers/interrupt_controller/Kconfig.multilevel"

source "drivers/interrupt_controller/Kconfig.s1000"

source "drivers/interrupt_controller/Kconfig.rv32m1"

source "drivers/interrupt_controller/Kconfig.sam0"

endmenu