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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 | /* * Copyright (c) 2018 Google LLC. * * SPDX-License-Identifier: Apache-2.0 */ #include <device.h> #include <soc.h> #include <drivers/dma.h> #include <logging/log.h> LOG_MODULE_REGISTER(dma_sam0, CONFIG_DMA_LOG_LEVEL); #define DMA_REGS ((Dmac *)DT_INST_0_ATMEL_SAM0_DMAC_BASE_ADDRESS) typedef void (*dma_callback)(void *callback_arg, u32_t channel, int error_code); struct dma_sam0_channel { dma_callback cb; void *cb_arg; }; struct dma_sam0_data { __aligned(16) DmacDescriptor descriptors[DMAC_CH_NUM]; __aligned(16) DmacDescriptor descriptors_wb[DMAC_CH_NUM]; struct dma_sam0_channel channels[DMAC_CH_NUM]; }; #define DEV_DATA(dev) \ ((struct dma_sam0_data *const)(dev)->driver_data) /* Handles DMA interrupts and dispatches to the individual channel */ static void dma_sam0_isr(void *arg) { struct device *dev = arg; struct dma_sam0_data *data = DEV_DATA(dev); struct dma_sam0_channel *chdata; u16_t pend = DMA_REGS->INTPEND.reg; u32_t channel; /* Acknowledge all interrupts for the channel in pend */ DMA_REGS->INTPEND.reg = pend; channel = (pend & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; chdata = &data->channels[channel]; if (pend & DMAC_INTPEND_TERR) { if (chdata->cb) { chdata->cb(chdata->cb_arg, channel, -DMAC_INTPEND_TERR); } } else if (pend & DMAC_INTPEND_TCMPL) { if (chdata->cb) { chdata->cb(chdata->cb_arg, channel, 0); } } /* * If more than one channel is pending, we'll just immediately * interrupt again and handle it through a different INTPEND value. */ } /* Configure a channel */ static int dma_sam0_config(struct device *dev, u32_t channel, struct dma_config *config) { struct dma_sam0_data *data = DEV_DATA(dev); DmacDescriptor *desc = &data->descriptors[channel]; struct dma_block_config *block = config->head_block; struct dma_sam0_channel *channel_control; DMAC_BTCTRL_Type btctrl = { .reg = 0 }; int key; if (channel >= DMAC_CH_NUM) { LOG_ERR("Unsupported channel"); return -EINVAL; } if (config->block_count > 1) { LOG_ERR("Chained transfers not supported"); /* TODO: add support for chained transfers. */ return -ENOTSUP; } if (config->dma_slot >= DMAC_TRIG_NUM) { LOG_ERR("Invalid trigger number"); return -EINVAL; } /* Lock and page in the channel configuration */ key = irq_lock(); /* * The "bigger" DMAC on some SAM0 chips (e.g. SAMD5x) has * independently accessible registers for each channel, while * the other ones require an indirect channel selection before * accessing shared registers. The simplest way to detect the * difference is the presence of the DMAC_CHID_ID macro from the * ASF HAL (i.e. it's only defined if indirect access is required). */ #ifdef DMAC_CHID_ID /* Select the channel for configuration */ DMA_REGS->CHID.reg = DMAC_CHID_ID(channel); DMA_REGS->CHCTRLA.reg = 0; /* Connect the peripheral trigger */ if (config->channel_direction == MEMORY_TO_MEMORY) { /* * A single software trigger will start the * transfer */ DMA_REGS->CHCTRLB.reg = DMAC_CHCTRLB_TRIGACT_TRANSACTION | DMAC_CHCTRLB_TRIGSRC(config->dma_slot); } else { /* One peripheral trigger per beat */ DMA_REGS->CHCTRLB.reg = DMAC_CHCTRLB_TRIGACT_BEAT | DMAC_CHCTRLB_TRIGSRC(config->dma_slot); } /* Set the priority */ if (config->channel_priority >= DMAC_LVL_NUM) { LOG_ERR("Invalid priority"); goto inval; } DMA_REGS->CHCTRLB.bit.LVL = config->channel_priority; /* Enable the interrupts */ DMA_REGS->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; if (!config->error_callback_en) { DMA_REGS->CHINTENSET.reg = DMAC_CHINTENSET_TERR; } else { DMA_REGS->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; } DMA_REGS->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_TCMPL; #else /* Channels have separate configuration registers */ DmacChannel * chcfg = &DMA_REGS->Channel[channel]; if (config->channel_direction == MEMORY_TO_MEMORY) { /* * A single software trigger will start the * transfer */ chcfg->CHCTRLA.reg = DMAC_CHCTRLA_TRIGACT_TRANSACTION | DMAC_CHCTRLA_TRIGSRC(config->dma_slot); } else { /* One peripheral trigger per beat */ chcfg->CHCTRLA.reg = DMAC_CHCTRLA_TRIGACT_BLOCK | DMAC_CHCTRLA_TRIGSRC(config->dma_slot); } /* Set the priority */ if (config->channel_priority >= DMAC_LVL_NUM) { LOG_ERR("Invalid priority"); goto inval; } chcfg->CHPRILVL.bit.PRILVL = config->channel_priority; /* Enable the interrupts */ chcfg->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; if (!config->error_callback_en) { chcfg->CHINTENSET.reg = DMAC_CHINTENSET_TERR; } else { chcfg->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; } chcfg->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR | DMAC_CHINTFLAG_TCMPL; #endif /* Set the beat (single transfer) size */ if (config->source_data_size != config->dest_data_size) { LOG_ERR("Source and destination data sizes must be equal"); goto inval; } switch (config->source_data_size) { case 1: btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_BYTE_Val; break; case 2: btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_HWORD_Val; break; case 4: btctrl.bit.BEATSIZE = DMAC_BTCTRL_BEATSIZE_WORD_Val; break; default: LOG_ERR("Invalid data size"); goto inval; } /* Set up the one and only block */ desc->BTCNT.reg = block->block_size / config->source_data_size; desc->DESCADDR.reg = 0; /* Set the automatic source / dest increment */ switch (block->source_addr_adj) { case DMA_ADDR_ADJ_INCREMENT: desc->SRCADDR.reg = block->source_address + block->block_size; btctrl.bit.SRCINC = 1; break; case DMA_ADDR_ADJ_NO_CHANGE: desc->SRCADDR.reg = block->source_address; break; default: LOG_ERR("Invalid source increment"); goto inval; } switch (block->dest_addr_adj) { case DMA_ADDR_ADJ_INCREMENT: desc->DSTADDR.reg = block->dest_address + block->block_size; btctrl.bit.DSTINC = 1; break; case DMA_ADDR_ADJ_NO_CHANGE: desc->DSTADDR.reg = block->dest_address; break; default: LOG_ERR("Invalid destination increment"); goto inval; } btctrl.bit.VALID = 1; desc->BTCTRL = btctrl; channel_control = &data->channels[channel]; channel_control->cb = config->dma_callback; channel_control->cb_arg = config->callback_arg; LOG_DBG("Configured channel %d for %08X to %08X (%u)", channel, block->source_address, block->dest_address, block->block_size); irq_unlock(key); return 0; inval: irq_unlock(key); return -EINVAL; } static int dma_sam0_start(struct device *dev, u32_t channel) { int key = irq_lock(); ARG_UNUSED(dev); #ifdef DMAC_CHID_ID DMA_REGS->CHID.reg = channel; DMA_REGS->CHCTRLA.reg = DMAC_CHCTRLA_ENABLE; if (DMA_REGS->CHCTRLB.bit.TRIGSRC == 0) { /* Trigger via software */ DMA_REGS->SWTRIGCTRL.reg = 1U << channel; } #else DmacChannel * chcfg = &DMA_REGS->Channel[channel]; chcfg->CHCTRLA.bit.ENABLE = 1; if (chcfg->CHCTRLA.bit.TRIGSRC == 0) { /* Trigger via software */ DMA_REGS->SWTRIGCTRL.reg = 1U << channel; } #endif irq_unlock(key); return 0; } static int dma_sam0_stop(struct device *dev, u32_t channel) { int key = irq_lock(); ARG_UNUSED(dev); #ifdef DMAC_CHID_ID DMA_REGS->CHID.reg = channel; DMA_REGS->CHCTRLA.reg = 0; #else DmacChannel * chcfg = &DMA_REGS->Channel[channel]; chcfg->CHCTRLA.bit.ENABLE = 0; #endif irq_unlock(key); return 0; } static int dma_sam0_reload(struct device *dev, u32_t channel, u32_t src, u32_t dst, size_t size) { struct dma_sam0_data *data = DEV_DATA(dev); DmacDescriptor *desc = &data->descriptors[channel]; int key = irq_lock(); switch (desc->BTCTRL.bit.BEATSIZE) { case DMAC_BTCTRL_BEATSIZE_BYTE_Val: desc->BTCNT.reg = size; break; case DMAC_BTCTRL_BEATSIZE_HWORD_Val: desc->BTCNT.reg = size / 2U; break; case DMAC_BTCTRL_BEATSIZE_WORD_Val: desc->BTCNT.reg = size / 4U; break; default: goto inval; } if (desc->BTCTRL.bit.SRCINC) { desc->SRCADDR.reg = src + size; } else { desc->SRCADDR.reg = src; } if (desc->BTCTRL.bit.DSTINC) { desc->DSTADDR.reg = dst + size; } else { desc->DSTADDR.reg = dst; } LOG_DBG("Reloaded channel %d for %08X to %08X (%u)", channel, src, dst, size); irq_unlock(key); return 0; inval: irq_unlock(key); return -EINVAL; } static int dma_sam0_get_status(struct device *dev, u32_t channel, struct dma_status *stat) { struct dma_sam0_data *data = DEV_DATA(dev); u32_t act; if (channel >= DMAC_CH_NUM || stat == NULL) { return -EINVAL; } act = DMA_REGS->ACTIVE.reg; if ((act & DMAC_ACTIVE_ABUSY) && ((act & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos) == channel) { stat->busy = true; stat->pending_length = (act & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; } else { stat->busy = false; stat->pending_length = data->descriptors_wb[channel].BTCNT.reg; } switch (data->descriptors[channel].BTCTRL.bit.BEATSIZE) { case DMAC_BTCTRL_BEATSIZE_BYTE_Val: break; case DMAC_BTCTRL_BEATSIZE_HWORD_Val: stat->pending_length *= 2U; break; case DMAC_BTCTRL_BEATSIZE_WORD_Val: stat->pending_length *= 4U; break; default: return -EINVAL; } return 0; } DEVICE_DECLARE(dma_sam0_0); #define DMA_SAM0_IRQ_CONNECT(n) \ do { \ IRQ_CONNECT(DT_INST_0_ATMEL_SAM0_DMAC_IRQ_ ## n, \ DT_INST_0_ATMEL_SAM0_DMAC_IRQ_ ## n ## _PRIORITY, \ dma_sam0_isr, DEVICE_GET(dma_sam0_0), 0); \ irq_enable(DT_INST_0_ATMEL_SAM0_DMAC_IRQ_ ## n); \ } while (0) static int dma_sam0_init(struct device *dev) { struct dma_sam0_data *data = DEV_DATA(dev); /* Enable clocks. */ #ifdef MCLK MCLK->AHBMASK.bit.DMAC_ = 1; #else PM->AHBMASK.bit.DMAC_ = 1; PM->APBBMASK.bit.DMAC_ = 1; #endif /* Set up the descriptor and write back addresses */ DMA_REGS->BASEADDR.reg = (uintptr_t)&data->descriptors; DMA_REGS->WRBADDR.reg = (uintptr_t)&data->descriptors_wb; /* Statically map each level to the same numeric priority */ DMA_REGS->PRICTRL0.reg = DMAC_PRICTRL0_LVLPRI0(0) | DMAC_PRICTRL0_LVLPRI1(1) | DMAC_PRICTRL0_LVLPRI2(2) | DMAC_PRICTRL0_LVLPRI3(3); /* Enable the unit and enable all priorities */ DMA_REGS->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0x0F); #ifdef DT_INST_0_ATMEL_SAM0_DMAC_IRQ_0 DMA_SAM0_IRQ_CONNECT(0); #endif #ifdef DT_INST_0_ATMEL_SAM0_DMAC_IRQ_1 DMA_SAM0_IRQ_CONNECT(1); #endif #ifdef DT_INST_0_ATMEL_SAM0_DMAC_IRQ_2 DMA_SAM0_IRQ_CONNECT(2); #endif #ifdef DT_INST_0_ATMEL_SAM0_DMAC_IRQ_3 DMA_SAM0_IRQ_CONNECT(3); #endif #ifdef DT_INST_0_ATMEL_SAM0_DMAC_IRQ_4 DMA_SAM0_IRQ_CONNECT(4); #endif return 0; } static struct dma_sam0_data dmac_data; static const struct dma_driver_api dma_sam0_api = { .config = dma_sam0_config, .start = dma_sam0_start, .stop = dma_sam0_stop, .reload = dma_sam0_reload, .get_status = dma_sam0_get_status, }; DEVICE_AND_API_INIT(dma_sam0_0, CONFIG_DMA_0_NAME, &dma_sam0_init, &dmac_data, NULL, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &dma_sam0_api); |