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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 | /* * Copyright (c) 2010-2014 Wind River Systems, Inc. * * SPDX-License-Identifier: Apache-2.0 */ /** * @file * @brief Interrupt management support for IA-32 architecture * * This module implements assembly routines to manage interrupts on * the Intel IA-32 architecture. More specifically, the interrupt (asynchronous * exception) stubs are implemented in this module. The stubs are invoked when * entering and exiting a C interrupt handler. */ #include <kernel_structs.h> #include <arch/x86/ia32/asm.h> #include <offsets_short.h> #include <arch/cpu.h> #include <drivers/interrupt_controller/sysapic.h> /* exports (internal APIs) */ GTEXT(_interrupt_enter) GTEXT(z_SpuriousIntNoErrCodeHandler) GTEXT(z_SpuriousIntHandler) GTEXT(_irq_sw_handler) GTEXT(z_dynamic_stubs_begin) /* externs */ GTEXT(__swap) #ifdef CONFIG_SYS_POWER_MANAGEMENT GTEXT(z_sys_power_save_idle_exit) #endif /** * * @brief Inform the kernel of an interrupt * * This function is called from the interrupt stub created by IRQ_CONNECT() * to inform the kernel of an interrupt. This routine increments * _kernel.nested (to support interrupt nesting), switches to the * base of the interrupt stack, if not already on the interrupt stack, and then * saves the volatile integer registers onto the stack. Finally, control is * returned back to the interrupt stub code (which will then invoke the * "application" interrupt service routine). * * Only the volatile integer registers are saved since ISRs are assumed not to * utilize floating point (or SSE) instructions. * * WARNINGS * * Host-based tools and the target-based GDB agent depend on the stack frame * created by this routine to determine the locations of volatile registers. * These tools must be updated to reflect any changes to the stack frame. * * @return N/A * * C function prototype: * * void _interrupt_enter(void *isr, void *isr_param); */ SECTION_FUNC(TEXT, _interrupt_enter) /* * Note that the processor has pushed both the EFLAGS register * and the logical return address (cs:eip) onto the stack prior * to invoking the handler specified in the IDT. The stack looks * like this: * * 24 SS (only on privilege level change) * 20 ESP (only on privilege level change) * 16 EFLAGS * 12 CS * 8 EIP * 4 isr_param * 0 isr <-- stack pointer */ #ifdef CONFIG_EXECUTION_BENCHMARKING pushl %eax pushl %edx rdtsc mov %eax, __start_intr_time mov %edx, __start_intr_time+4 pop %edx pop %eax #endif /* * The gen_idt tool creates an interrupt-gate descriptor for * all connections. The processor will automatically clear the IF * bit in the EFLAGS register upon execution of the handler, hence * this need not issue an 'cli' as the first instruction. * * Clear the direction flag. It is automatically restored when the * interrupt exits via the IRET instruction. */ cld #ifdef CONFIG_X86_KPTI call z_x86_trampoline_to_kernel #endif /* * Swap EAX with isr_param and EDX with isr. * Push ECX onto the stack */ xchgl %eax, 4(%esp) xchgl %edx, (%esp) pushl %ecx /* Now the stack looks like: * * EFLAGS * CS * EIP * saved EAX * saved EDX * saved ECX * * EAX = isr_param, EDX = isr */ /* Push EDI as we will use it for scratch space. * Rest of the callee-saved regs get saved by invocation of C * functions (isr handler, __swap(), etc) */ pushl %edi #if defined(CONFIG_TRACING) /* Save these as we are using to keep track of isr and isr_param */ pushl %eax pushl %edx call z_sys_trace_isr_enter popl %edx popl %eax #endif /* load %ecx with &_kernel */ movl $_kernel, %ecx /* switch to the interrupt stack for the non-nested case */ incl _kernel_offset_to_nested(%ecx) /* use interrupt stack if not nested */ cmpl $1, _kernel_offset_to_nested(%ecx) jne alreadyOnIntStack /* * switch to base of the interrupt stack: save esp in edi, then load * irq_stack pointer */ movl %esp, %edi movl _kernel_offset_to_irq_stack(%ecx), %esp /* save thread's stack pointer onto base of interrupt stack */ pushl %edi /* Save stack pointer */ #ifdef CONFIG_SYS_POWER_MANAGEMENT cmpl $0, _kernel_offset_to_idle(%ecx) jne handle_idle /* fast path is !idle, in the pipeline */ #endif /* CONFIG_SYS_POWER_MANAGEMENT */ /* fall through to nested case */ alreadyOnIntStack: #ifndef CONFIG_X86_IAMCU /* EAX has the interrupt handler argument, needs to go on * stack for sys V calling convention */ push %eax #endif #ifdef CONFIG_EXECUTION_BENCHMARKING /* Save the eax and edx registers before reading the time stamp * once done pop the values */ pushl %eax pushl %edx rdtsc mov %eax,__end_intr_time mov %edx,__end_intr_time+4 pop %edx pop %eax #endif #ifdef CONFIG_NESTED_INTERRUPTS sti /* re-enable interrupts */ #endif /* Now call the interrupt handler */ INDIRECT_CALL(%edx) #ifndef CONFIG_X86_IAMCU /* Discard ISR argument */ addl $0x4, %esp #endif #ifdef CONFIG_NESTED_INTERRUPTS cli /* disable interrupts again */ #endif #if defined(CONFIG_X2APIC) call z_x2apic_eoi #else /* xAPIC EOI */ xorl %eax, %eax movl %eax, (CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) #endif /* determine whether exiting from a nested interrupt */ movl $_kernel, %ecx decl _kernel_offset_to_nested(%ecx) /* dec interrupt nest count */ jne nestedInterrupt /* 'iret' if nested case */ #ifdef CONFIG_PREEMPT_ENABLED movl _kernel_offset_to_current(%ecx), %edx /* reschedule only if the scheduler says that we must do so */ cmpl %edx, _kernel_offset_to_ready_q_cache(%ecx) je noReschedule /* * Set the _INT_ACTIVE bit in the k_thread to allow the upcoming call to * __swap() to determine whether non-floating registers need to be * preserved using the lazy save/restore algorithm, or to indicate to * debug tools that a preemptive context switch has occurred. */ #if defined(CONFIG_LAZY_FP_SHARING) orb $_INT_ACTIVE, _thread_offset_to_thread_state(%edx) #endif /* * A context reschedule is required: keep the volatile registers of * the interrupted thread on the context's stack. Utilize * the existing __swap() primitive to save the remaining * thread's registers (including floating point) and perform * a switch to the new thread. */ popl %esp /* switch back to outgoing thread's stack */ #ifdef CONFIG_STACK_SENTINEL call z_check_stack_sentinel #endif pushfl /* push KERNEL_LOCK_KEY argument */ #ifdef CONFIG_X86_IAMCU /* IAMCU first argument goes into a register, not the stack. */ popl %eax #endif call __swap #ifndef CONFIG_X86_IAMCU addl $4, %esp /* pop KERNEL_LOCK_KEY argument */ #endif /* * The interrupted thread has now been scheduled, * as the result of a _later_ invocation of __swap(). * * Now need to restore the interrupted thread's environment before * returning control to it at the point where it was interrupted ... */ #if defined(CONFIG_LAZY_FP_SHARING) /* * __swap() has restored the floating point registers, if needed. * Clear the _INT_ACTIVE bit in the interrupted thread's state * since it has served its purpose. */ movl _kernel + _kernel_offset_to_current, %eax andb $~_INT_ACTIVE, _thread_offset_to_thread_state(%eax) #endif /* CONFIG_LAZY_FP_SHARING */ /* Restore volatile registers and return to the interrupted thread */ popl %edi popl %ecx popl %edx popl %eax /* Pop of EFLAGS will re-enable interrupts and restore direction flag */ KPTI_IRET #endif /* CONFIG_PREEMPT_ENABLED */ noReschedule: /* * A thread reschedule is not required; switch back to the * interrupted thread's stack and restore volatile registers */ popl %esp /* pop thread stack pointer */ #ifdef CONFIG_STACK_SENTINEL call z_check_stack_sentinel #endif /* fall through to 'nestedInterrupt' */ /* * For the nested interrupt case, the interrupt stack must still be * utilized, and more importantly, a rescheduling decision must * not be performed. */ nestedInterrupt: popl %edi popl %ecx /* pop volatile registers in reverse order */ popl %edx popl %eax /* Pop of EFLAGS will re-enable interrupts and restore direction flag */ KPTI_IRET #ifdef CONFIG_SYS_POWER_MANAGEMENT handle_idle: pushl %eax pushl %edx /* Populate 'ticks' argument to z_sys_power_save_idle_exit */ #ifdef CONFIG_X86_IAMCU movl _kernel_offset_to_idle(%ecx), %eax #else /* SYS V calling convention */ push _kernel_offset_to_idle(%ecx) #endif /* Zero out _kernel.idle */ movl $0, _kernel_offset_to_idle(%ecx) /* * Beware that a timer driver's z_sys_power_save_idle_exit() implementation might * expect that interrupts are disabled when invoked. This ensures that * the calculation and programming of the device for the next timer * deadline is not interrupted. */ call z_sys_power_save_idle_exit #ifndef CONFIG_X86_IAMCU /* SYS V: discard 'ticks' argument passed on the stack */ add $0x4, %esp #endif popl %edx popl %eax jmp alreadyOnIntStack #endif /* CONFIG_SYS_POWER_MANAGEMENT */ /** * * z_SpuriousIntHandler - * @brief Spurious interrupt handler stubs * * Interrupt-gate descriptors are statically created for all slots in the IDT * that point to z_SpuriousIntHandler() or z_SpuriousIntNoErrCodeHandler(). The * former stub is connected to exception vectors where the processor pushes an * error code onto the stack (or kernel stack) in addition to the EFLAGS/CS/EIP * records. * * A spurious interrupt is considered a fatal condition; there is no provision * to return to the interrupted execution context and thus the volatile * registers are not saved. * * @return Never returns * * C function prototype: * * void z_SpuriousIntHandler (void); * * INTERNAL * The gen_idt tool creates an interrupt-gate descriptor for all * connections. The processor will automatically clear the IF bit * in the EFLAGS register upon execution of the handler, * thus z_SpuriousIntNoErrCodeHandler()/z_SpuriousIntHandler() shall be * invoked with interrupts disabled. */ SECTION_FUNC(TEXT, z_SpuriousIntNoErrCodeHandler) pushl $0 /* push dummy err code onto stk */ /* fall through to z_SpuriousIntHandler */ SECTION_FUNC(TEXT, z_SpuriousIntHandler) cld /* Clear direction flag */ /* Create the ESF */ pushl %eax pushl %ecx pushl %edx pushl %edi pushl %esi pushl %ebx pushl %ebp leal 44(%esp), %ecx /* Calculate ESP before exception occurred */ pushl %ecx /* Save calculated ESP */ #ifndef CONFIG_X86_IAMCU pushl %esp /* push cur stack pointer: pEsf arg */ #else mov %esp, %eax #endif /* re-enable interrupts */ sti /* call the fatal error handler */ call z_x86_spurious_irq /* handler doesn't return */ #if CONFIG_IRQ_OFFLOAD SECTION_FUNC(TEXT, _irq_sw_handler) push $0 push $z_irq_do_offload jmp _interrupt_enter #endif #if CONFIG_X86_DYNAMIC_IRQ_STUBS > 0 z_dynamic_irq_stub_common: /* stub number already pushed */ push $z_x86_dynamic_irq_handler jmp _interrupt_enter /* Create all the dynamic IRQ stubs * * NOTE: Please update DYN_STUB_SIZE in include/arch/x86/ia32/arch.h if you * change how large the generated stubs are, otherwise _get_dynamic_stub() * will be unable to correctly determine the offset */ /* * Create nice labels for all the stubs so we can see where we * are in a debugger */ .altmacro .macro __INT_STUB_NUM id z_dynamic_irq_stub_\id: .endm .macro INT_STUB_NUM id __INT_STUB_NUM %id .endm z_dynamic_stubs_begin: stub_num = 0 .rept ((CONFIG_X86_DYNAMIC_IRQ_STUBS + Z_DYN_STUB_PER_BLOCK - 1) / Z_DYN_STUB_PER_BLOCK) block_counter = 0 .rept Z_DYN_STUB_PER_BLOCK .if stub_num < CONFIG_X86_DYNAMIC_IRQ_STUBS INT_STUB_NUM stub_num /* * 2-byte push imm8. */ push $stub_num /* * Check to make sure this isn't the last stub in * a block, in which case we just fall through */ .if (block_counter <> (Z_DYN_STUB_PER_BLOCK - 1) && \ (stub_num <> CONFIG_X86_DYNAMIC_IRQ_STUBS - 1)) /* This should always be a 2-byte jmp rel8 */ jmp 1f .endif stub_num = stub_num + 1 block_counter = block_counter + 1 .endif .endr /* * This must a 5-bvte jump rel32, which is why z_dynamic_irq_stub_common * is before the actual stubs */ 1: jmp z_dynamic_irq_stub_common .endr #endif /* CONFIG_X86_DYNAMIC_IRQ_STUBS > 0 */ |