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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 | /* * Copyright (c) 2011-2015 Wind River Systems, Inc. * * SPDX-License-Identifier: Apache-2.0 */ /** * @file * @brief Exception management support for IA-32 architecture * * This module implements assembly routines to manage exceptions (synchronous * interrupts) on the Intel IA-32 architecture. More specifically, * exceptions are implemented in this module. The stubs are invoked when entering * and exiting a C exception handler. */ #include <kernel_structs.h> #include <arch/x86/ia32/asm.h> #include <arch/x86/ia32/arch.h> /* For MK_ISR_NAME */ #include <offsets_short.h> /* exports (internal APIs) */ GTEXT(_exception_enter) GTEXT(_kernel_oops_handler) /* externs (internal APIs) */ GTEXT(z_do_kernel_oops) /** * * @brief Inform the kernel of an exception * * This function is called from the exception stub created by nanoCpuExcConnect() * to inform the kernel of an exception. This routine currently does * _not_ increment a thread/interrupt specific exception count. Also, * execution of the exception handler occurs on the current stack, i.e. * this does not switch to another stack. The volatile integer * registers are saved on the stack, and control is returned back to the * exception stub. * * WARNINGS * * Host-based tools and the target-based GDB agent depend on the stack frame * created by this routine to determine the locations of volatile registers. * These tools must be updated to reflect any changes to the stack frame. * * @return N/A * * C function prototype: * * void _exception_enter(u32_t error_code, void *handler) * */ SECTION_FUNC(TEXT, _exception_enter) /* * The gen_idt tool creates an interrupt-gate descriptor for * all connections. The processor will automatically clear the IF * bit in the EFLAGS register upon execution of the handler, thus * this does need not issue an 'cli' as the first instruction. * * Note that the processor has pushed both the EFLAGS register * and the linear return address (cs:eip) onto the stack prior * to invoking the handler specified in the IDT. * * Clear the direction flag. It is automatically restored when the * exception exits. */ cld #ifdef CONFIG_X86_KPTI call z_x86_trampoline_to_kernel #endif /* * Swap ecx and handler function on the current stack; */ xchgl %ecx, (%esp) /* By the time we get here, the stack should look like this: * ESP -> ECX (excepting task) * Exception Error code (or junk) * EIP (excepting task) * CS (excepting task) * EFLAGS (excepting task) * ... * * ECX now contains the address of the handler function */ /* * Push the remaining volatile registers on the existing stack. */ pushl %eax pushl %edx /* * Push the cooperative registers on the existing stack as they are * required by debug tools. */ pushl %edi pushl %esi pushl %ebx pushl %ebp #ifdef CONFIG_USERSPACE /* Test if interrupted context was in ring 3 */ testb $3, 36(%esp) jz 1f /* It was. The original stack pointer is on the stack 44 bytes * from the current top */ pushl 44(%esp) jmp 2f 1: #endif leal 44(%esp), %eax /* Calculate ESP before interrupt occurred */ pushl %eax /* Save calculated ESP */ #ifdef CONFIG_USERSPACE 2: #endif /* ESP is pointing to the ESF at this point */ #if defined(CONFIG_LAZY_FP_SHARING) movl _kernel + _kernel_offset_to_current, %edx /* inc exception nest count */ incl _thread_offset_to_excNestCount(%edx) /* * Set the _EXC_ACTIVE state bit of the current thread. * This enables z_swap() to preserve the thread's FP registers * (where needed) if the exception handler causes a context switch. * It also indicates to debug tools that an exception is being * handled in the event of a context switch. */ orb $_EXC_ACTIVE, _thread_offset_to_thread_state(%edx) #endif /* CONFIG_LAZY_FP_SHARING */ /* * restore interrupt enable state, then call the handler * * interrupts are enabled only if they were allowed at the time * the exception was triggered -- this protects kernel level code * that mustn't be interrupted * * Test IF bit of saved EFLAGS and re-enable interrupts if IF=1. */ /* ESP is still pointing to the ESF at this point */ testl $0x200, __z_arch_esf_t_eflags_OFFSET(%esp) je allDone sti allDone: #if CONFIG_X86_IAMCU movl %esp, %eax /* z_arch_esf_t * parameter */ #else pushl %esp /* push z_arch_esf_t * parameter */ #endif INDIRECT_CALL(%ecx) /* call exception handler */ #ifndef CONFIG_X86_IAMCU addl $0x4, %esp #endif #if defined(CONFIG_LAZY_FP_SHARING) movl _kernel + _kernel_offset_to_current, %ecx /* * Must lock interrupts to prevent outside interference. * (Using "lock" prefix would be nicer, but this won't work * on platforms that don't respect the CPU's bus lock signal.) */ cli /* * Determine whether exiting from a nested interrupt. */ decl _thread_offset_to_excNestCount(%ecx) cmpl $0, _thread_offset_to_excNestCount(%ecx) jne nestedException /* * Clear the _EXC_ACTIVE bit in the k_thread of the current execution * context if we are not in a nested exception (ie, when we exit the * outermost exception). */ andb $~_EXC_ACTIVE, _thread_offset_to_thread_state(%ecx) nestedException: #endif /* CONFIG_LAZY_FP_SHARING */ /* * Pop the non-volatile registers from the stack. * Note that debug tools may have altered the saved register values while * the task was stopped, and we want to pick up the altered values. */ popl %ebp /* Discard saved ESP */ popl %ebp popl %ebx popl %esi popl %edi /* restore edx and ecx which are always saved on the stack */ popl %edx popl %eax popl %ecx addl $4, %esp /* "pop" error code */ /* Pop of EFLAGS will re-enable interrupts and restore direction flag */ KPTI_IRET #if CONFIG_X86_KERNEL_OOPS SECTION_FUNC(TEXT, _kernel_oops_handler) push $0 /* dummy error code */ push $z_do_kernel_oops jmp _exception_enter #endif |